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Searched refs:LSC_CHICKEN_BIT_0_UDW (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_wa.c325 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
340 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
357 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
362 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))
442 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
465 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
498 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
522 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
/linux-6.12.1/drivers/gpu/drm/i915/gt/
Dintel_workarounds.c2814 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, in general_render_compute_wa_init()
2836 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); in general_render_compute_wa_init()
2839 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3); in general_render_compute_wa_init()
2847 wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, in general_render_compute_wa_init()
Dintel_gt_regs.h1188 #define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4) macro
/linux-6.12.1/drivers/gpu/drm/xe/regs/
Dxe_gt_regs.h497 #define LSC_CHICKEN_BIT_0_UDW XE_REG_MCR(0xe7c8 + 4) macro