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Searched refs:LSC_CHICKEN_BIT_0 (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_wa.c330 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
347 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
397 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
438 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
461 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE))
518 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
539 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
/linux-6.12.1/drivers/gpu/drm/xe/regs/
Dxe_gt_regs.h490 #define LSC_CHICKEN_BIT_0 XE_REG_MCR(0xe7c8) macro
/linux-6.12.1/drivers/gpu/drm/i915/gt/
Dintel_workarounds.c2825 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); in general_render_compute_wa_init()
2852 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, in general_render_compute_wa_init()
Dintel_gt_regs.h1185 #define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8) macro