Searched refs:LC_LINK_WIDTH_RD_MASK (Results 1 – 11 of 11) sorted by relevance
953 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
1102 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
1509 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
370 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
2050 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in rv770_pcie_gen2_enable()
1487 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
904 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
4529 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in r600_pcie_gen2_enable()
4783 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK; in ci_get_current_pcie_lane_number()
1572 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
1524 switch ((link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT) { in si_get_pcie_lanes()