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Searched refs:L3_PWM_TIMER_INIT_VAL_MASK (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_tuning.c32 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
33 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
37 XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
38 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
112 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
113 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
131 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
132 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
/linux-6.12.1/drivers/gpu/drm/xe/regs/
Dxe_gt_regs.h387 #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0) macro
/linux-6.12.1/drivers/gpu/drm/i915/gt/
Dintel_workarounds.c682 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, in dg2_ctx_gt_tuning_init()
683 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); in dg2_ctx_gt_tuning_init()
Dintel_gt_regs.h1007 #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0) macro