Searched refs:IDENT_ADDR (Results 1 – 20 of 20) sorted by relevance
73 #define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL)75 #define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL)76 #define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL)101 #define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL)106 #define CIA_IOC_FLASH_CTRL (IDENT_ADDR + 0x8740000200UL)107 #define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL)108 #define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL)109 #define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL)110 #define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL)120 #define CIA_IOC_CIA_DIAG (IDENT_ADDR + 0x8740002000UL)[all …]
34 #define T2_CONF (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL)35 #define T2_IO (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL)36 #define T2_SPARSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL)37 #define T2_DENSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL)39 #define T2_IOCSR (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL)40 #define T2_CERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL)41 #define T2_CERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL)42 #define T2_CERR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL)43 #define T2_PERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL)44 #define T2_PERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL)[all …]
22 #define POLARIS_SPARSE_MEM_BASE (IDENT_ADDR + 0xf800000000UL)23 #define POLARIS_DENSE_MEM_BASE (IDENT_ADDR + 0xf900000000UL)24 #define POLARIS_SPARSE_IO_BASE (IDENT_ADDR + 0xf980000000UL)25 #define POLARIS_SPARSE_CONFIG_BASE (IDENT_ADDR + 0xf9c0000000UL)26 #define POLARIS_IACK_BASE (IDENT_ADDR + 0xf9f8000000UL)27 #define POLARIS_DENSE_IO_BASE (IDENT_ADDR + 0xf9fc000000UL)28 #define POLARIS_DENSE_CONFIG_BASE (IDENT_ADDR + 0xf9fe000000UL)
89 #define MCPCIA_SPARSE(m) (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m))90 #define MCPCIA_DENSE(m) (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m))91 #define MCPCIA_IO(m) (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m))92 #define MCPCIA_CONF(m) (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m))93 #define MCPCIA_CSR(m) (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m))94 #define MCPCIA_IO_IACK(m) (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m))95 #define MCPCIA_DENSE_IO(m) (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m))96 #define MCPCIA_DENSE_CONF(m) (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m))
89 #define TSUNAMI_cchip ((tsunami_cchip *)(IDENT_ADDR+TS_BIAS+0x1A0000000UL))90 #define TSUNAMI_dchip ((tsunami_dchip *)(IDENT_ADDR+TS_BIAS+0x1B0000800UL))91 #define TSUNAMI_pchip0 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x180000000UL))92 #define TSUNAMI_pchip1 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x380000000UL))257 #define TSUNAMI_BASE (IDENT_ADDR + TS_BIAS)
124 #define IRONGATE_MEM (IDENT_ADDR | IRONGATE_BIAS | 0x000000000UL)125 #define IRONGATE_IACK_SC (IDENT_ADDR | IRONGATE_BIAS | 0x1F8000000UL)126 #define IRONGATE_IO (IDENT_ADDR | IRONGATE_BIAS | 0x1FC000000UL)127 #define IRONGATE_CONF (IDENT_ADDR | IRONGATE_BIAS | 0x1FE000000UL)
127 #define TITAN_cchip ((titan_cchip *)(IDENT_ADDR+TI_BIAS+0x1A0000000UL))128 #define TITAN_dchip ((titan_dchip *)(IDENT_ADDR+TI_BIAS+0x1B0000800UL))129 #define TITAN_pachip0 ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x180000000UL))130 #define TITAN_pachip1 ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x380000000UL))299 #define TITAN_BASE (IDENT_ADDR + TI_BIAS)
203 = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT; in init_new_context()212 = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT; in enter_lazy_tlb()
21 #define IDENT_ADDR 0xffff800000000000UL macro23 #define IDENT_ADDR 0xfffffc0000000000UL macro61 return (unsigned long)address - IDENT_ADDR; in virt_to_phys()66 return (void *) (address + IDENT_ADDR); in phys_to_virt()85 return (void *)(IDENT_ADDR + (address & ((1ul << 41) - 1))); in phys_to_virt()
120 ~0UL : IDENT_ADDR + 0x01000000)
223 #define WILDFIRE_BASE (IDENT_ADDR | (1UL << 40))
54 #define EV7_KERN_ADDR(addr) ((void *)(IDENT_ADDR | EV7_MASK40(addr)))
169 hose->dense_mem_base = POLARIS_DENSE_MEM_BASE - IDENT_ADDR; in polaris_init_arch()171 hose->dense_io_base = POLARIS_DENSE_IO_BASE - IDENT_ADDR; in polaris_init_arch()
446 hose->sparse_mem_base = T2_SPARSE_MEM - IDENT_ADDR; in t2_init_arch()447 hose->dense_mem_base = T2_DENSE_MEM - IDENT_ADDR; in t2_init_arch()448 hose->sparse_io_base = T2_IO - IDENT_ADDR; in t2_init_arch()
704 hose->sparse_mem_base = CIA_SPARSE_MEM - IDENT_ADDR; in do_init_arch()705 hose->dense_mem_base = CIA_DENSE_MEM - IDENT_ADDR; in do_init_arch()706 hose->sparse_io_base = CIA_IO - IDENT_ADDR; in do_init_arch()710 hose->dense_mem_base = CIA_BW_MEM - IDENT_ADDR; in do_init_arch()712 hose->dense_io_base = CIA_BW_IO - IDENT_ADDR; in do_init_arch()
304 hose->sparse_mem_base = MCPCIA_SPARSE(mid) - IDENT_ADDR; in mcpcia_new_hose()305 hose->dense_mem_base = MCPCIA_DENSE(mid) - IDENT_ADDR; in mcpcia_new_hose()306 hose->sparse_io_base = MCPCIA_IO(mid) - IDENT_ADDR; in mcpcia_new_hose()
245 (IDENT_ADDR | pcpu->console_data_log_pa); in cdl_process_console_data_log()
818 if (!__direct_map_base && MAX_DMA_ADDRESS - IDENT_ADDR - 1 <= mask) in alpha_pci_supported()
719 addr = IDENT_ADDR | (baddr - __direct_map_base); in marvel_ioremap()
52 pcb->ptbr = ((unsigned long) next_mm->pgd - IDENT_ADDR) >> PAGE_SHIFT; in __load_new_mm_context()