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Searched refs:HDMI_ACR_CTS_32 (Results 1 – 16 of 16) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.h182 SE_SF(HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
260 SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
454 uint8_t HDMI_ACR_CTS_32; member
586 uint32_t HDMI_ACR_CTS_32; member
Ddce_stream_encoder.c1300 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); in dce110_se_setup_hdmi_audio()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn32/
Ddcn32_dio_stream_encoder.h77 SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn401/
Ddcn401_dio_stream_encoder.h79 SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn10/
Ddcn10_stream_encoder.h252 SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
468 type HDMI_ACR_CTS_32;\
Ddcn10_stream_encoder.c1286 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); in enc1_se_setup_hdmi_audio()
/linux-6.12.1/drivers/gpu/drm/radeon/
Devergreen_hdmi.c89 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); in evergreen_hdmi_update_acr()
Drv770d.h788 # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) macro
Devergreend.h642 # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) macro
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn35/
Ddcn35_dio_stream_encoder.h157 SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn30/
Ddcn30_dio_stream_encoder.h156 SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
Ddcn30_dio_stream_encoder.c791 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); in enc3_se_setup_hdmi_audio()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn314/
Ddcn314_dio_stream_encoder.h156 SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Ddce_v6_0.c1443 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); in dce_v6_0_audio_set_acr()
Ddce_v10_0.c1492 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); in dce_v10_0_afmt_update_ACR()
Ddce_v11_0.c1541 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); in dce_v11_0_afmt_update_ACR()