Searched refs:HDMI_ACR_32_1 (Results 1 – 17 of 17) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_stream_encoder.h | 78 SRI(HDMI_ACR_32_1, DIG, id),\
183 SE_SF(HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
679 uint32_t HDMI_ACR_32_1; member
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| D | dce_stream_encoder.c | 1303 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); in dce110_se_setup_hdmi_audio()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| D | dcn10_stream_encoder.h | 69 SRI(HDMI_ACR_32_1, DIG, id),\
162 uint32_t HDMI_ACR_32_1; member
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| D | dcn10_stream_encoder.c | 1289 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); in enc1_se_setup_hdmi_audio()
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| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | evergreen_hdmi.c | 90 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); in evergreen_hdmi_update_acr()
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| D | rv770d.h | 789 #define HDMI_ACR_32_1 0x74b0 macro
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| D | evergreend.h | 643 #define HDMI_ACR_32_1 0x70e0 macro
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| D | dcn35_resource.h | 102 SRI_ARR(HDMI_ACR_32_1, DIG, id),\
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn35/ |
| D | dcn35_dio_stream_encoder.h | 70 SRI(HDMI_ACR_32_1, DIG, id),\
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
| D | dcn30_dio_stream_encoder.h | 71 SRI(HDMI_ACR_32_1, DIG, id),\
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| D | dcn30_dio_stream_encoder.c | 794 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); in enc3_se_setup_hdmi_audio()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn314/ |
| D | dcn314_dio_stream_encoder.h | 72 SRI(HDMI_ACR_32_1, DIG, id),\
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| D | dcn401_resource.h | 195 SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| D | dcn32_resource.h | 280 SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | dce_v6_0.c | 1446 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); in dce_v6_0_audio_set_acr()
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| D | dce_v10_0.c | 1495 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); in dce_v10_0_afmt_update_ACR()
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| D | dce_v11_0.c | 1544 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); in dce_v11_0_afmt_update_ACR()
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