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Searched refs:HDMI_ACR_32_0 (Results 1 – 17 of 17) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.h77 SRI(HDMI_ACR_32_0, DIG, id),\
182 SE_SF(HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
678 uint32_t HDMI_ACR_32_0; member
Ddce_stream_encoder.c1300 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); in dce110_se_setup_hdmi_audio()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn10/
Ddcn10_stream_encoder.h68 SRI(HDMI_ACR_32_0, DIG, id),\
161 uint32_t HDMI_ACR_32_0; member
Ddcn10_stream_encoder.c1286 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); in enc1_se_setup_hdmi_audio()
/linux-6.12.1/drivers/gpu/drm/radeon/
Devergreen_hdmi.c89 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); in evergreen_hdmi_update_acr()
Drv770d.h787 #define HDMI_ACR_32_0 0x74ac macro
Devergreend.h641 #define HDMI_ACR_32_0 0x70dc macro
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn35/
Ddcn35_resource.h101 SRI_ARR(HDMI_ACR_32_0, DIG, id),\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn35/
Ddcn35_dio_stream_encoder.h69 SRI(HDMI_ACR_32_0, DIG, id),\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn30/
Ddcn30_dio_stream_encoder.h70 SRI(HDMI_ACR_32_0, DIG, id),\
Ddcn30_dio_stream_encoder.c791 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); in enc3_se_setup_hdmi_audio()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn314/
Ddcn314_dio_stream_encoder.h71 SRI(HDMI_ACR_32_0, DIG, id),\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn401/
Ddcn401_resource.h195 SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/
Ddcn32_resource.h280 SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Ddce_v6_0.c1443 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); in dce_v6_0_audio_set_acr()
Ddce_v10_0.c1492 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); in dce_v10_0_afmt_update_ACR()
Ddce_v11_0.c1541 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); in dce_v11_0_afmt_update_ACR()