Searched refs:GCC_VIDEO_AXI0_CLK_ARES (Results 1 – 15 of 15) sorted by relevance
| /linux-6.12.1/include/dt-bindings/clock/ |
| D | qcom,gcc-sm8450.h | 233 #define GCC_VIDEO_AXI0_CLK_ARES 34 macro
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| D | qcom,sm8550-gcc.h | 217 #define GCC_VIDEO_AXI0_CLK_ARES 33 macro
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| D | qcom,sm8650-gcc.h | 240 #define GCC_VIDEO_AXI0_CLK_ARES 33 macro
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| D | qcom,gcc-sm8350.h | 249 #define GCC_VIDEO_AXI0_CLK_ARES 35 macro
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| D | qcom,gcc-sm8250.h | 255 #define GCC_VIDEO_AXI0_CLK_ARES 43 macro
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| D | qcom,sa8775p-gcc.h | 306 #define GCC_VIDEO_AXI0_CLK_ARES 44 macro
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| D | qcom,gcc-sc8280xp.h | 479 #define GCC_VIDEO_AXI0_CLK_ARES 77 macro
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| /linux-6.12.1/drivers/clk/qcom/ |
| D | gcc-sm8450.c | 3205 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x42018, .bit = 2, .udelay = 1000 },
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| D | gcc-sm8550.c | 3279 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 },
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| D | gcc-sm8250.c | 3579 [GCC_VIDEO_AXI0_CLK_ARES] = { 0xb024, .bit = 2, .udelay = 150 },
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| D | gcc-sm8650.c | 3737 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 },
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| D | gcc-sm8350.c | 3746 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x28010, .bit = 2, .udelay = 400 },
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| D | gcc-sa8775p.c | 4598 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x34014, .bit = 2, .udelay = 400 },
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| D | gcc-sc8280xp.c | 7451 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x28010, .bit = 2, .udelay = 400 },
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| /linux-6.12.1/arch/arm64/boot/dts/qcom/ |
| D | sm8250.dtsi | 4324 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
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