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Searched refs:DP_TP_CTL (Results 1 – 5 of 5) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_fdi.c925 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
986 intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0); in hsw_fdi_link_train()
987 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
999 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
Dintel_ddi.c2195 return DP_TP_CTL(encoder->port); in dp_tp_ctl_reg()
/linux-6.12.1/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c526 MMIO_D(DP_TP_CTL(PORT_A)); in iterate_generic_mmio()
527 MMIO_D(DP_TP_CTL(PORT_B)); in iterate_generic_mmio()
528 MMIO_D(DP_TP_CTL(PORT_C)); in iterate_generic_mmio()
529 MMIO_D(DP_TP_CTL(PORT_D)); in iterate_generic_mmio()
530 MMIO_D(DP_TP_CTL(PORT_E)); in iterate_generic_mmio()
Di915_reg.h3816 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) macro
/linux-6.12.1/drivers/gpu/drm/i915/gvt/
Dhandlers.c829 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); in fdi_auto_training_started()
949 calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))
2356 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2357 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2358 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2359 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2360 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()