Searched refs:DISP_CC_MDSS_CORE_BCR (Results 1 – 25 of 27) sorted by relevance
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| /linux-6.12.1/include/dt-bindings/clock/ |
| D | qcom,dispcc-qcm2290.h | 36 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| D | qcom,sm6375-dispcc.h | 36 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| D | qcom,sm4450-dispcc.h | 47 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| D | qcom,dispcc-sm8150.h | 70 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| D | qcom,dispcc-sm8350.h | 70 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| D | qcom,dispcc-sm8250.h | 70 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| D | qcom,dispcc-sc8280xp.h | 93 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| D | qcom,x1e80100-dispcc.h | 90 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| D | qcom,sm8550-dispcc.h | 93 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| D | qcom,sm8650-dispcc.h | 93 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| D | qcom,sm8450-dispcc.h | 95 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| /linux-6.12.1/drivers/clk/qcom/ |
| D | dispcc-qcm2290.c | 449 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
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| D | dispcc-sm6375.c | 544 [DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
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| D | dispcc-sm4450.c | 712 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
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| D | dispcc-sm8250.c | 1220 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
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| D | dispcc-x1e80100.c | 1620 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
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| D | dispcc-sm8450.c | 1719 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
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| D | dispcc-sm8550.c | 1724 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
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| D | dispcc-sc8280xp.c | 3047 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
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| /linux-6.12.1/arch/arm64/boot/dts/qcom/ |
| D | qcm2290.dtsi | 1597 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| D | sc8280xp.dtsi | 4107 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
5394 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
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| D | sc8180x.dtsi | 2946 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| D | sm8350.dtsi | 2507 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| D | sm8450.dtsi | 3063 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| D | sm8550.dtsi | 2870 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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