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Searched refs:CLK_TOP_MSDC50_0_HCLK (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dmt6779-clk.h18 #define CLK_TOP_MSDC50_0_HCLK 8 macro
Dmt8186-clk.h31 #define CLK_TOP_MSDC50_0_HCLK 12 macro
Dmediatek,mt8188-clk.h37 #define CLK_TOP_MSDC50_0_HCLK 26 macro
Dmt8195-clk.h41 #define CLK_TOP_MSDC50_0_HCLK 29 macro
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt8186-topckgen.c534 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
Dclk-mt8188-topckgen.c1017 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
Dclk-mt8195-topckgen.c944 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc50_0_hclk",
Dclk-mt6779.c688 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",