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Searched refs:CLK_SCLK_MPLL (Results 1 – 5 of 5) sorted by relevance

/linux-6.12.1/arch/arm/boot/dts/samsung/
Dexynos4210-trats.dts220 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
228 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
236 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
244 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
Dexynos4210-universal_c210.dts234 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
242 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
250 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
258 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
Dexynos4210-i9100.dts341 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
350 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
358 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
367 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
/linux-6.12.1/include/dt-bindings/clock/
Dexynos4.h21 #define CLK_SCLK_MPLL 9 macro
/linux-6.12.1/drivers/clk/samsung/
Dclk-exynos4.c467 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
544 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
1255 CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_SCLK_MPLL,
1388 clk_hw_get_rate(hws[CLK_SCLK_MPLL]), in exynos4_clk_init()