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Searched refs:CLK_INFRA_PWM_SEL (Results 1 – 2 of 2) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dmediatek,mt7988-clk.h147 #define CLK_INFRA_PWM_SEL 6 macro
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt7988-infracfg.c71 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,