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Searched refs:CLK_APMIXED_MMPLL (Results 1 – 25 of 35) sorted by relevance

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/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt8186-apmixedsys.c63 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0254, 0x0260, 0,
126 FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x008C),
Dclk-mt6795-apmixedsys.c53 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, 0x244, 0),
107 FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c),
Dclk-mt8173-apmixedsys.c69 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0,
126 FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c),
Dclk-mt8195-apmixedsys.c74 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x00e0, 0x00f0, 0xff000000,
157 FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0),
Dclk-mt8192-apmixedsys.c81 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0360, 0x036c, 0xff000000,
139 FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0),
Dclk-mt7988-apmixed.c52 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4,
Dclk-mt8135-apmixedsys.c42 …PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, …
Dclk-mt7986-apmixed.c47 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x0, 0, 32,
Dclk-mt7981-apmixed.c49 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
Dclk-mt8516-apmixedsys.c66 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0,
Dclk-mt8167-apmixedsys.c65 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0,
Dclk-mt8188-apmixedsys.c69 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0544, 0x0550, 0xff000000,
Dclk-mt2712-apmixedsys.c102 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100,
Dclk-mt8365-apmixedsys.c93 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0330, 0x033C, 0x00000001, 0, 22,
Dclk-mt8183-apmixedsys.c133 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0,
/linux-6.12.1/include/dt-bindings/clock/
Dmt7986-clk.h14 #define CLK_APMIXED_MMPLL 2 macro
Dmt8135-clk.h112 #define CLK_APMIXED_MMPLL 5 macro
Dmediatek,mt7981-clk.h190 #define CLK_APMIXED_MMPLL 2 macro
Dmt8516-clk.h16 #define CLK_APMIXED_MMPLL 3 macro
Dmediatek,mt7988-clk.h15 #define CLK_APMIXED_MMPLL 2 macro
Dmediatek,mt6795-clk.h144 #define CLK_APMIXED_MMPLL 3 macro
Dmt8173-clk.h160 #define CLK_APMIXED_MMPLL 5 macro
Dmt6765-clk.h15 #define CLK_APMIXED_MMPLL 5 macro
Dmediatek,mt8365-clk.h236 #define CLK_APMIXED_MMPLL 5 macro
Dmt6779-clk.h174 #define CLK_APMIXED_MMPLL 9 macro

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