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Searched full:sys_pll (Results 1 – 10 of 10) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/clock/
Damlogic,a1-peripherals-clkc.yaml34 minItems: 6 # sys_pll is optional
44 - const: sys_pll
45 minItems: 6 # sys_pll is optional
76 "hifi_pll", "xtal", "sys_pll";
/linux-6.12.1/arch/arm/boot/dts/arm/
Dvexpress-v2p-ca15-tc1.dts81 clocks = <&sys_pll>;
90 clocks = <&sys_pll>, <&sys_pll>;
111 clocks = <&sys_pll>;
123 clocks = <&sys_pll>;
181 sys_pll: clock-controller-7 { label
/linux-6.12.1/drivers/clk/microchip/
Dclk-pic32mzda.c49 "sys_pll", "refi" #__clkid "_clk", \
85 "frcdiv_clk", "sys_pll", "posc_clk",
96 static const struct pic32_sys_pll_data sys_pll = { variable
101 .name = "sys_pll",
208 clks[PLLCLK] = pic32_spll_clk_register(&sys_pll, core); in pic32mzda_clk_probe()
Dclk-core.c754 dev_err(core->dev, "sys_pll: clk_register() failed\n"); in pic32_spll_clk_register()
/linux-6.12.1/arch/nios2/boot/dts/
D10m50_devboard.dts145 sys_pll: clock@1 { label
153 clock-output-names = "sys_pll-c0";
160 clock-output-names = "sys_pll-c1";
167 clock-output-names = "sys_pll-c2";
/linux-6.12.1/drivers/clk/meson/
Dg12a.c151 .name = "sys_pll",
231 * This clock is used to debug the sys_pll range
250 * This clock is used to debug the sys_pll range
1046 struct clk_hw *sys_pll; member
1060 * This notifier means sys_pll clock will be changed in g12a_sys_pll_notifier_cb()
1063 * \- sys_pll in g12a_sys_pll_notifier_cb()
1088 * The sys_pll has ben updated, now switch back cpu_clk to in g12a_sys_pll_notifier_cb()
1089 * sys_pll in g12a_sys_pll_notifier_cb()
1092 /* Configure cpu_clk to use sys_pll */ in g12a_sys_pll_notifier_cb()
1094 nb_data->sys_pll); in g12a_sys_pll_notifier_cb()
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Daxg.c138 .name = "sys_pll",
Dgxbb.c421 .name = "sys_pll",
Dmeson8b.c307 .name = "sys_pll",
/linux-6.12.1/drivers/clk/pistachio/
Dclk-pistachio.c117 PNAME(mux_xtal_sys) = { "xtal", "sys_pll" };
149 PLL_FIXED(CLK_SYS_PLL, "sys_pll", "xtal", PLL_GF40LP_FRAC, 0x38),