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/linux-6.12.1/drivers/clk/imx/
Dclk-scu.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2021 NXP
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
10 #include <linux/clk-provider.h>
20 #include "clk-scu.h"
44 * struct clk_scu - Description of one SCU clock
46 * @rsrc_id: resource ID of this SCU clock
62 * struct clk_gpr_scu - Description of one SCU GPR clock
64 * @rsrc_id: resource ID of this SCU clock
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 mxc-clk-objs += clk.o
4 mxc-clk-objs += clk-busy.o
5 mxc-clk-objs += clk-composite-7ulp.o
6 mxc-clk-objs += clk-composite-8m.o
7 mxc-clk-objs += clk-composite-93.o
8 mxc-clk-objs += clk-fracn-gppll.o
9 mxc-clk-objs += clk-cpu.o
10 mxc-clk-objs += clk-divider-gate.o
11 mxc-clk-objs += clk-fixup-div.o
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Dclk-lpcg-scu.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
14 #include "clk-scu.h"
23 * struct clk_lpcg_scu - Description of LPCG clock
46 struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw); in clk_lpcg_scu_enable() local
52 reg = readl_relaxed(clk->reg); in clk_lpcg_scu_enable()
53 reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); in clk_lpcg_scu_enable()
56 if (clk->hw_gate) in clk_lpcg_scu_enable()
59 reg |= val << clk->bit_idx; in clk_lpcg_scu_enable()
60 writel(reg, clk->reg); in clk_lpcg_scu_enable()
[all …]
Dclk-imx8qxp.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2021 NXP
7 #include <linux/clk-provider.h>
15 #include "clk-scu.h"
17 #include <dt-bindings/firmware/imx/rsrc.h>
127 return of_device_is_compatible(node, "fsl,imx8dxl-clk"); in clk_on_imx8dxl()
132 struct device_node *ccm_node = pdev->dev.of_node; in imx8qxp_clk_probe()
136 rsrc_table = of_device_get_match_data(&pdev->dev); in imx8qxp_clk_probe()
239 /* MIPI-LVDS SS */ in imx8qxp_clk_probe()
334 { .compatible = "fsl,scu-clk", },
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Dclk-imx8dxl-rsrc.c1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include "clk-scu.h"
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dfsl,scu-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX SCU Client Device Node - Clock Controller Based on SCU Message Protocol
10 - Abel Vesa <abel.vesa@nxp.com>
12 description: i.MX SCU Client Device Node
13 Client nodes are maintained as children of the relevant IMX-SCU device node.
15 (Documentation/devicetree/bindings/clock/clock-bindings.txt)
18 include/dt-bindings/clock/imx8qxp-clock.h
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Dairoha,en7523-scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/airoha,en7523-scu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felix Fietkau <nbd@nbd.name>
11 - John Crispin <nbd@nbd.name>
25 [1]: <include/dt-bindings/clock/en7523-clk.h>.
32 - enum:
33 - airoha,en7523-scu
34 - airoha,en7581-scu
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/linux-6.12.1/Documentation/devicetree/bindings/firmware/
Dfsl,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
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/linux-6.12.1/drivers/gpu/drm/aspeed/
Daspeed_gfx_drv.c1 // SPDX-License-Identifier: GPL-2.0+
4 #include <linux/clk.h>
5 #include <linux/dma-mapping.h>
61 u32 dac_reg; /* DAC register in SCU */
63 u32 vga_scratch_reg; /* VGA scratch register in SCU */
93 { .compatible = "aspeed,ast2400-gfx", .data = &ast2400_config },
94 { .compatible = "aspeed,ast2500-gfx", .data = &ast2500_config },
95 { .compatible = "aspeed,ast2600-gfx", .data = &ast2600_config },
114 drm->mode_config.min_width = 0; in aspeed_gfx_setup_mode_config()
115 drm->mode_config.min_height = 0; in aspeed_gfx_setup_mode_config()
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/linux-6.12.1/drivers/soc/aspeed/
Daspeed-lpc-ctrl.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk.h>
17 #include <linux/aspeed-lpc-ctrl.h>
19 #define DEVICE_NAME "aspeed-lpc-ctrl"
34 struct clk *clk; member
40 struct regmap *scu; member
45 return container_of(file->private_data, struct aspeed_lpc_ctrl, in file_aspeed_lpc_ctrl()
52 unsigned long vsize = vma->vm_end - vma->vm_start; in aspeed_lpc_ctrl_mmap()
53 pgprot_t prot = vma->vm_page_prot; in aspeed_lpc_ctrl_mmap()
55 if (vma->vm_pgoff + vma_pages(vma) > lpc_ctrl->mem_size >> PAGE_SHIFT) in aspeed_lpc_ctrl_mmap()
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/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8dxl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/clock/imx8-lpcg.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/pads-imx8dxl.h>
14 #include <dt-bindings/thermal/thermal.h>
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Dimx8qxp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2020 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/clock/imx8-lpcg.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
Dimx8qm.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/pads-imx8qm.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
[all …]
Dimx8-ss-dma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/dma/fsl-edma.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
11 dma_ipg_clk: clock-dma-ipg {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <120000000>;
15 clock-output-names = "dma_ipg_clk";
[all …]
/linux-6.12.1/drivers/pinctrl/
Dpinctrl-lpc18xx.c2 * Pinctrl driver for NXP LPC18xx/LPC43xx System Control Unit (SCU)
12 #include <linux/clk.h>
18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
26 /* LPC18XX SCU analog function registers */
32 /* LPC18XX SCU pin register definitions */
54 /* LPC18XX SCU pin interrupt select registers */
68 TYPE_ND, /* Normal-drive */
69 TYPE_HD, /* High-drive */
70 TYPE_HS, /* High-speed */
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/can/
Dfsl,flexcan.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
11 - Marc Kleine-Budde <mkl@pengutronix.de>
14 - $ref: can-controller.yaml#
19 - enum:
20 - fsl,imx95-flexcan
21 - fsl,imx93-flexcan
22 - fsl,imx8qm-flexcan
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/linux-6.12.1/drivers/clk/
Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
48 /* clk rst name parent flags */
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
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/linux-6.12.1/drivers/clk/renesas/
Dr8a7795-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 * Based on clk-rcar-gen3.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
133 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
134 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
149 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
[all …]
Dr8a7791-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Glider bvba
7 * Based on clk-rcar-gen2.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen2-cpg.h"
96 DEF_MOD("2d-dmac", 115, R8A7791_CLK_ZS),
97 DEF_MOD("fdp1-1", 118, R8A7791_CLK_ZS),
98 DEF_MOD("fdp1-0", 119, R8A7791_CLK_ZS),
[all …]
Dr8a7790-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on clk-rcar-gen2.c
15 #include <linux/soc/renesas/rcar-rst.h>
17 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
19 #include "renesas-cpg-mssr.h"
20 #include "rcar-gen2-cpg.h"
101 DEF_MOD("2d-dmac", 115, R8A7790_CLK_ZS),
102 DEF_MOD("fdp1-2", 117, R8A7790_CLK_ZS),
103 DEF_MOD("fdp1-1", 118, R8A7790_CLK_ZS),
104 DEF_MOD("fdp1-0", 119, R8A7790_CLK_ZS),
[all …]
Dr8a7794-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on clk-rcar-gen2.c
15 #include <linux/soc/renesas/rcar-rst.h>
17 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
19 #include "renesas-cpg-mssr.h"
20 #include "rcar-gen2-cpg.h"
93 DEF_MOD("2d-dmac", 115, R8A7794_CLK_ZS),
94 DEF_MOD("fdp1-0", 119, R8A7794_CLK_ZS),
109 DEF_MOD("sys-dmac1", 218, R8A7794_CLK_ZS),
110 DEF_MOD("sys-dmac0", 219, R8A7794_CLK_ZS),
[all …]
/linux-6.12.1/arch/arm/boot/dts/airoha/
Den7523.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/en7523-clk.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
13 reserved-memory {
14 #address-cells = <1>;
[all …]
/linux-6.12.1/drivers/iio/adc/
Daspeed_adc.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
178 struct regmap *scu; in aspeed_adc_set_trim_data() local
184 dev_warn(data->dev, "Couldn't find syscon node\n"); in aspeed_adc_set_trim_data()
185 return -EOPNOTSUPP; in aspeed_adc_set_trim_data()
187 scu = syscon_node_to_regmap(syscon); in aspeed_adc_set_trim_data()
189 if (IS_ERR(scu)) { in aspeed_adc_set_trim_data()
190 dev_warn(data->dev, "Failed to get syscon regmap\n"); in aspeed_adc_set_trim_data()
191 return -EOPNOTSUPP; in aspeed_adc_set_trim_data()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/arm/cpu-enable-method/
Dnuvoton,npcm750-smp2 Secondary CPU enable-method "nuvoton,npcm750-smp" binding
5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
8 Enable method name: "nuvoton,npcm750-smp"
10 Compatible CPUs: "arm,cortex-a9"
14 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
15 "nuvoton,npcm750-gcr".
20 #address-cells = <1>;
21 #size-cells = <0>;
22 enable-method = "nuvoton,npcm750-smp";
26 compatible = "arm,cortex-a9";
[all …]
/linux-6.12.1/drivers/pmdomain/imx/
Dscu-pd.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
7 * Implementation of the SCU based Power Domains
10 * single global power domain and implement the ->attach|detach_dev()
12 * From within the ->attach_dev(), we could get the OF node for
13 * the device that is being attached and then parse the power-domain
18 * Additionally, we need to implement the ->stop() and ->start()
20 * rather than using the above ->power_on|off() callbacks.
23 * 1. The ->attach_dev() of power domain infrastructure still does
32 * Update: Genpd assigns the ->of_node for the virtual device before it
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