Home
last modified time | relevance | path

Searched +full:r8a779f0 +full:- +full:ether +full:- +full:serdes (Results 1 – 7 of 7) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/phy/
Drenesas,r8a779f0-ether-serdes.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,r8a779f0-ether-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Ethernet SERDES
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
14 const: renesas,r8a779f0-ether-serdes
25 power-domains:
28 '#phy-cells':
29 description: Port number of SERDES.
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Drenesas,r8a779f0-ether-switch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,r8a779f0-ether-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
14 const: renesas,r8a779f0-ether-switch
19 reg-names:
21 - const: base
22 - const: secure_base
27 interrupt-names:
[all …]
/linux-6.12.1/drivers/phy/renesas/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_R8A779F0_ETHERNET_SERDES) += r8a779f0-ether-serdes.o
3 obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
4 obj-$(CONFIG_PHY_RCAR_GEN3_PCIE) += phy-rcar-gen3-pcie.o
5 obj-$(CONFIG_PHY_RCAR_GEN3_USB2) += phy-rcar-gen3-usb2.o
6 obj-$(CONFIG_PHY_RCAR_GEN3_USB3) += phy-rcar-gen3-usb3.o
Dr8a779f0-ether-serdes.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Renesas Ethernet SERDES device driver
59 iowrite32(bank, channel->addr + R8A779F0_ETH_SERDES_BANK_SELECT); in r8a779f0_eth_serdes_reg_wait()
61 ret = readl_poll_timeout_atomic(channel->addr + offs, val, in r8a779f0_eth_serdes_reg_wait()
65 dev_dbg(&channel->phy->dev, in r8a779f0_eth_serdes_reg_wait()
67 __func__, channel->index, offs, bank, mask, expected); in r8a779f0_eth_serdes_reg_wait()
79 channel = &dd->channel[i]; in r8a779f0_eth_serdes_common_init_ram()
85 r8a779f0_eth_serdes_write32(dd->addr, 0x026c, 0x180, 0x03); in r8a779f0_eth_serdes_common_init_ram()
93 struct r8a779f0_eth_serdes_drv_data *dd = channel->dd; in r8a779f0_eth_serdes_common_setting()
95 switch (channel->phy_interface) { in r8a779f0_eth_serdes_common_setting()
[all …]
/linux-6.12.1/drivers/clk/renesas/
Dr8a779f0-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a779f0 Clock Pulse Generator / Module Standby and Software Reset
7 * Based on r8a779a0-cpg-mssr.c
12 #include <linux/clk-provider.h>
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen4-cpg.h"
152 DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER),
153 DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER),
[all …]
/linux-6.12.1/arch/arm64/boot/dts/renesas/
Dr8a779f0.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779f0-sysc.h>
13 compatible = "renesas,r8a779f0";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 cluster01_opp: opp-table-0 {
18 compatible = "operating-points-v2";
[all …]
/linux-6.12.1/drivers/net/ethernet/renesas/
Drswitch.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/dma-mapping.h>
45 iowrite32(RRC_RR, priv->addr + RRC); in rswitch_reset()
46 iowrite32(RRC_RR_CLR, priv->addr + RRC); in rswitch_reset()
51 iowrite32(RCEC_ACE_DEFAULT | RCEC_RCE, priv->addr + RCEC); in rswitch_clock_enable()
56 iowrite32(RCDC_RCD, priv->addr + RCDC); in rswitch_clock_disable()
88 val = ioread32(priv->addr + CABPIRM); in rswitch_bpool_config()
92 iowrite32(CABPIRM_BPIOG, priv->addr + CABPIRM); in rswitch_bpool_config()
94 return rswitch_reg_wait(priv->addr, CABPIRM, CABPIRM_BPR, CABPIRM_BPR); in rswitch_bpool_config()
99 iowrite32(CABPPFLC_INIT_VALUE, priv->addr + CABPPFLC0); in rswitch_coma_init()
[all …]