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/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dcdns,qspi-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vaishnav Achath <vaishnav.a@ti.com>
13 - $ref: spi-controller.yaml#
14 - if:
18 const: xlnx,versal-ospi-1.0
21 - power-domains
22 - if:
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/linux-6.12.1/arch/arm/boot/dts/intel/socfpga/
Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
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/linux-6.12.1/drivers/spi/
Dspi-cadence-quadspi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // Driver for Cadence QSPI Controller
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
30 #include <linux/spi/spi-mem.h>
33 #define CQSPI_NAME "cadence-qspi"
314 if (ret != -ETIMEDOUT) in cqspi_wait_for_bit()
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/linux-6.12.1/drivers/bus/
Domap_l3_noc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
44 /* 1 0 1 */ "Write Non-Posted",
50 * struct l3_masters_data - L3 Master information
60 * struct l3_target_data - L3 Target information
72 * struct l3_flagmux_data - Flag Mux information
91 * struct omap_l3 - Description of data relevant for L3 bus.
315 {0x3900, "QSPI",},
450 { 0x0, "M1 (128-bit)"},
451 { 0x1, "M2 (64-bit)"},
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/linux-6.12.1/arch/arm64/boot/dts/intel/
Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
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/linux-6.12.1/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Ddra7.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
21 interrupt-parent = <&crossbar_mpu>;
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Dam4372.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/am4.h>
15 interrupt-parent = <&wakeupgen>;
16 #address-cells = <1>;
17 #size-cells = <1>;
37 spi0 = &qspi;
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/linux-6.12.1/arch/riscv/boot/dts/starfive/
Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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