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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
[all …]
/linux-6.12.1/arch/arm64/boot/dts/arm/
Dfoundation-v8-gicv3.dtsi8 gic: interrupt-controller@2f000000 { label
9 compatible = "arm,gic-v3";
10 #interrupt-cells = <3>;
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-controller;
22 its: msi-controller@2f020000 { label
23 compatible = "arm,gic-v3-its";
24 msi-controller;
25 #msi-cells = <1>;
Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
[all …]
/linux-6.12.1/drivers/irqchip/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_IRQCHIP) += irqchip.o
4 obj-$(CONFIG_AL_FIC) += irq-al-fic.o
5 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
6 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
7 obj-$(CONFIG_ATH79) += irq-ath79-misc.o
8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
9 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
10 obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o
11 obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o
[all …]
Dirq-gic-v3-its-fsl-mc-msi.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
19 .name = "ITS-fMSI",
33 out_id = of_node ? of_msi_map_id(&mc_dev->dev, of_node, mc_dev->icid) : in fsl_mc_msi_domain_get_msi_id()
34 iort_msi_map_id(&mc_dev->dev, mc_dev->icid); in fsl_mc_msi_domain_get_msi_id()
47 return -EINVAL; in its_fsl_mc_msi_prepare()
50 if (!(mc_bus_dev->flags & FSL_MC_IS_DPRC)) in its_fsl_mc_msi_prepare()
51 return -EINVAL; in its_fsl_mc_msi_prepare()
54 * Set the device Id to be passed to the GIC-ITS: in its_fsl_mc_msi_prepare()
59 info->scratchpad[0].ul = fsl_mc_msi_domain_get_msi_id(msi_domain, in its_fsl_mc_msi_prepare()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/hisilicon/
Dhip05.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/linux-6.12.1/arch/arm64/boot/dts/cavium/
Dthunder2-99xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (c) 2013-2016 Broadcom
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
21 #address-cells = <0x2>;
22 #size-cells = <0x0>;
28 enable-method = "psci";
[all …]
Dthunder-88xx.dtsi2 * Cavium Thunder DTS file - Thunder SoC description
6 * This file is dual-licensed: you can use it either under the terms
24 * MA 02110-1301 USA
51 compatible = "cavium,thunder-88xx";
52 interrupt-parent = <&gic0>;
53 #address-cells = <2>;
54 #size-cells = <2>;
57 compatible = "arm,psci-0.2";
62 #address-cells = <2>;
63 #size-cells = <0>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/amd/
Delba.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2022 Advanced Micro Devices, Inc.
6 #include <dt-bindings/gpio/gpio.h>
7 #include "dt-bindings/interrupt-controller/arm-gic.h"
11 compatible = "amd,pensando-elba";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
16 dma-coherent;
19 compatible = "fixed-clock";
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/perf/
Darm,smmu-v3-pmcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <robin.murphy@arm.com>
20 pattern: "^pmu@[0-9a-f]*"
23 - items:
24 - const: arm,mmu-600-pmcg
25 - const: arm,smmu-v3-pmcg
[all …]
/linux-6.12.1/arch/arm64/boot/dts/marvell/
Darmada-ap810-ap0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
14 compatible = "marvell,armada-ap810";
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
28 ap810-ap0 {
29 #address-cells = <2>;
30 #size-cells = <2>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/misc/
Dfsl,qoriq-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/iommu/
Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
[all …]
/linux-6.12.1/arch/arm64/boot/dts/amazon/
Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020, Amazon.com, Inc. or its affiliates. All Rights Reserved
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 model = "Amazon's Annapurna Labs Alpine v3";
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
[all …]
Dalpine-v2.dtsi2 * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 interrupt-parent = <&gic>;
43 #address-cells = <2>;
44 #size-cells = <2>;
[all …]
/linux-6.12.1/Documentation/virt/kvm/devices/
Darm-vgic.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_ARM_VGIC_V2 ARM Generic Interrupt Controller v2.0
13 controller, requiring emulated user-space devices to inject interrupts to the
18 device and guest ITS devices, see arm-vgic-v3.txt. It is not possible to
26 KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit)
27 Base address in the guest physical address space of the GIC distributor
31 KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit)
32 Base address in the guest physical address space of the GIC virtual cpu
39 -E2BIG Address outside of addressable IPA range
40 -EINVAL Incorrectly aligned address
[all …]
/linux-6.12.1/include/kvm/
Darm_vgic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
21 #include <linux/irqchip/arm-gic-v4.h>
29 #define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
33 #define KVM_IRQCHIP_NUM_PINS (1020 - 32)
44 /* same for all guests, as depending only on the _host's_ GIC model */
46 /* type of the host GIC */
81 /* GIC system register CPU interface */
91 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
99 * Per-irq ops overriding some common behavious.
101 * Always called in non-preemptible section and the functions can use
[all …]
/linux-6.12.1/tools/testing/selftests/kvm/lib/aarch64/
Dgic_v3_its.c1 // SPDX-License-Identifier: GPL-2.0
3 * Guest ITS library, generously donated by drivers/irqchip/irq-gic-v3-its.c
14 #include "gic.h"
51 GUEST_FAIL("Couldn't find an ITS BASER of type %u", type); in its_find_baser()
52 return -1; in its_find_baser()
60 baser = ((size / SZ_64K) - 1) | in its_install_table()
74 cbaser = ((size / SZ_4K) - 1) | in its_install_cmdq()
108 cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]); in its_fixup_cmd()
109 cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]); in its_fixup_cmd()
110 cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]); in its_fixup_cmd()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
[all …]
Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/broadcom/stingray/
Dstingray.dtsi4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
16 * * Neither the name of Broadcom nor the names of its
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a72";
49 enable-method = "psci";
[all …]
/linux-6.12.1/arch/arm64/kvm/vgic/
Dvgic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 #include <linux/irqchip/arm-gic-common.h>
14 #define VGIC_ADDR_UNDEF (-1)
19 #define VGIC_LPI_MAX_INTID ((1 << INTERRUPT_ID_BITS_ITS) - 1)
47 * As per Documentation/virt/kvm/devices/arm-vgic-v3.rst,
68 * As per Documentation/virt/kvm/devices/arm-vgic-its.rst,
69 * below macros are defined for ITS table entry encoding.
105 return vcpu->kvm->arch.vgic.implementation_rev; in vgic_get_implementation_rev()
111 if (irq->config == VGIC_CONFIG_EDGE) in irq_is_pending()
112 return irq->pending_latch; in irq_is_pending()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/intel/
Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/remoteproc/
Dqcom,wcnss-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,wcnss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
21 - items:
22 - enum:
23 - qcom,pronto-v1-pil
24 - qcom,pronto-v2-pil
25 - qcom,pronto-v3-pil
[all …]

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