Searched full:gicr (Results 1 – 25 of 76) sorted by relevance
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| /linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic-v3.yaml | 76 - GIC Redistributors (GICR), one range per redistributor region
179 GICR registers when the GIC redistributors are powered off.
250 <0x2f100000 0x200000>, // GICR
278 <0x2d000000 0x800000>, // GICR 1: CPUs 0-31
279 <0x2e000000 0x800000>, // GICR 2: CPUs 32-63
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| /linux-6.12.1/drivers/irqchip/ |
| D | irq-gic-v3.c | 1873 /* Find the chips based on GICR regions PHYS addr */ in gic_enable_quirk_nvidia_t241()
2300 rdist_regs[i].redist_base = gic_of_iomap(node, 1 + i, "GICR", &res); in gic_of_init()
2371 pr_err("Couldn't map GICR region @%llx\n", redist->base_address); in gic_acpi_parse_madt_redist()
2379 gic_request_region(redist->base_address, redist->length, "GICR"); in gic_acpi_parse_madt_redist()
2402 * Virtual hotplug systems can use the MADT's "always-on" GICR entries. in gic_acpi_parse_madt_gicc()
2417 gic_request_region(gicc->gicr_base_address, size, "GICR"); in gic_acpi_parse_madt_gicc()
2440 /* Collect redistributor base addresses in GICR entries */ in gic_acpi_collect_gicr_base()
2444 pr_info("No valid GICR entries exist\n"); in gic_acpi_collect_gicr_base()
2462 * If GICC is enabled and has valid gicr base address, then it means in gic_acpi_match_gicc()
2463 * GICR base is presented via GICC. The redistributor is only known to in gic_acpi_match_gicc()
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| /linux-6.12.1/arch/arm64/boot/dts/intel/ |
| D | keembay-soc.dtsi | 58 <0x0 0x20580000 0x0 0x80000>; /* GICR */
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| /linux-6.12.1/arch/arm64/boot/dts/marvell/ |
| D | armada-ap810-ap0.dtsi | 52 <0x3060000 0x100000>, /* GICR */
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| D | ac5-98dx25xx.dtsi | 338 <0x0 0x80660000 0x0 0x40000>; /* GICR */
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| D | armada-37xx.dtsi | 489 <0x1d40000 0x40000>, /* GICR */
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| /linux-6.12.1/Documentation/arch/arm64/ |
| D | cpu-hotplug.rst | 66 ``enabled``. The 'always on' GICR structure must be used to describe the
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| /linux-6.12.1/arch/arm64/boot/dts/cavium/ |
| D | thunder2-99xx.dtsi | 67 <0x04 0x01000000 0x0 0x1000000>; /* GICR */
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| D | thunder-88xx.dtsi | 389 <0x8010 0x80000000 0x0 0x600000>; /* GICR */
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| /linux-6.12.1/arch/arm64/include/asm/ |
| D | acpi.h | 64 #define CPUIDLE_GICR_CTXT BIT(2) /* GICR */
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| /linux-6.12.1/arch/arm64/boot/dts/amd/ |
| D | elba.dtsi | 147 <0x0 0xa00000 0x0 0x200000>, /* GICR */
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| /linux-6.12.1/arch/arm64/boot/dts/mediatek/ |
| D | mt7988a.dtsi | 73 <0 0x0c080000 0 0x200000>, /* GICR */
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| D | mt7981b.dtsi | 53 <0 0x0c080000 0 0x200000>; /* GICR */
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| D | mt6779.dtsi | 126 <0 0x0c040000 0 0x200000>; /* GICR */
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| D | mt6797.dtsi | 480 <0 0x19200000 0 0x200000>, /* GICR */
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| /linux-6.12.1/arch/arm64/boot/dts/sprd/ |
| D | ums9620.dtsi | 174 <0x0 0x12040000 0 0x100000>; /* GICR */
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| D | sc9863a.dtsi | 159 <0x0 0x14040000 0 0x100000>; /* GICR */
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| /linux-6.12.1/arch/arm64/boot/dts/amazon/ |
| D | alpine-v2.dtsi | 120 <0x0 0xf0280000 0x0 0x200000>, /* GICR */
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| D | alpine-v3.dtsi | 326 <0x0 0xf0a00000 0 0x200000>, /* GICR */
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| /linux-6.12.1/arch/arm64/boot/dts/freescale/ |
| D | imx8dxl.dtsi | 90 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
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| D | imx8qxp.dtsi | 157 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
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| /linux-6.12.1/arch/arm64/boot/dts/hisilicon/ |
| D | hip05.dtsi | 247 <0x0 0x8d100000 0 0x300000>, /* GICR */
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| D | hip07.dtsi | 950 <0x0 0x4d100000 0x0 0x400000>, /* p0 GICR node 0 */
951 <0x0 0x6d100000 0x0 0x400000>, /* p0 GICR node 1 */
952 <0x400 0x4d100000 0x0 0x400000>, /* p1 GICR node 2 */
953 <0x400 0x6d100000 0x0 0x400000>, /* p1 GICR node 3 */
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| /linux-6.12.1/arch/arm64/boot/dts/arm/ |
| D | fvp-base-revc.dts | 198 <0x0 0x2f100000 0 0x200000>, // GICR
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| /linux-6.12.1/arch/arm64/boot/dts/microchip/ |
| D | sparx5.dtsi | 117 <0x6 0x00340000 0xc0000>, /* GICR */
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