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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dimx8ulp-cgc-clock.yaml14 under the control of several CGCs & PCCs modules. The CGC modules generate
Dimx8ulp-pcc-clock.yaml14 under the control of several CGCs & PCCs modules. The PCC modules control
/linux-6.12.1/drivers/ufs/host/
Dufs-qcom.c402 * The UTP controller has a number of internal clock gating cells (CGCs).
403 * Internal hardware sub-modules within the UTP controller control the CGCs.
404 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
405 * in a specific operation, UTP controller CGCs are by default disabled and