| /linux-6.12.1/Documentation/devicetree/bindings/clock/ti/ |
| D | apll.txt | 1 Binding for Texas Instruments APLL clock.
4 register-mapped APLL with usually two selectable input clocks
8 modes (locked, low power stop etc.) APLL mostly behaves like
15 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
18 - reg : address and length of the register set for controlling the APLL.
32 compatible = "ti,dra7-apll-clock";
37 compatible = "ti,omap2-apll-clock";
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| /linux-6.12.1/sound/soc/mediatek/mt8365/ |
| D | mt8365-afe-clk.c | 322 int mt8365_afe_enable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll) in mt8365_afe_enable_apll_tuner_cfg() argument
328 afe_priv->apll_tuner_ref_cnt[apll]++; in mt8365_afe_enable_apll_tuner_cfg()
329 if (afe_priv->apll_tuner_ref_cnt[apll] != 1) { in mt8365_afe_enable_apll_tuner_cfg()
334 if (apll == MT8365_AFE_APLL1) { in mt8365_afe_enable_apll_tuner_cfg()
350 int mt8365_afe_disable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll) in mt8365_afe_disable_apll_tuner_cfg() argument
356 afe_priv->apll_tuner_ref_cnt[apll]--; in mt8365_afe_disable_apll_tuner_cfg()
357 if (afe_priv->apll_tuner_ref_cnt[apll] == 0) { in mt8365_afe_disable_apll_tuner_cfg()
358 if (apll == MT8365_AFE_APLL1) in mt8365_afe_disable_apll_tuner_cfg()
365 } else if (afe_priv->apll_tuner_ref_cnt[apll] < 0) { in mt8365_afe_disable_apll_tuner_cfg()
366 afe_priv->apll_tuner_ref_cnt[apll] = 0; in mt8365_afe_disable_apll_tuner_cfg()
[all …]
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| D | mt8365-afe-clk.h | 28 int mt8365_afe_enable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll);
29 int mt8365_afe_disable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll);
30 int mt8365_afe_enable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll);
31 int mt8365_afe_disable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll);
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| /linux-6.12.1/sound/soc/mediatek/mt8186/ |
| D | mt8186-afe-clk.h | 14 /* APLL */
57 /* apll related mux */
97 int mt8186_get_apll_rate(struct mtk_base_afe *afe, int apll);
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| D | mt8186-dai-tdm.c | 22 unsigned int rate; /* for determine which apll to use */
222 /* which apll */ in mtk_afe_tdm_mclk_apll_connect()
253 /* which apll */ in mtk_afe_tdm_apll_connect()
256 /* choose APLL from tdm rate */ in mtk_afe_tdm_apll_connect()
339 int apll; in mtk_dai_tdm_cal_mclk() local
342 apll = mt8186_get_apll_by_rate(afe, freq); in mtk_dai_tdm_cal_mclk()
343 apll_rate = mt8186_get_apll_rate(afe, apll); in mtk_dai_tdm_cal_mclk()
353 "%s(), APLL cannot generate %d Hz", __func__, freq); in mtk_dai_tdm_cal_mclk()
358 tdm_priv->mclk_apll = apll; in mtk_dai_tdm_cal_mclk()
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| D | mt8186-afe-clk.c | 392 /* setting for APLL */ in mt8186_apll1_enable()
445 /* setting for APLL */ in mt8186_apll2_enable()
493 int mt8186_get_apll_rate(struct mtk_base_afe *afe, int apll) in mt8186_get_apll_rate() argument
495 return (apll == MT8186_APLL1) ? 180633600 : 196608000; in mt8186_get_apll_rate()
543 int apll = mt8186_get_apll_by_rate(afe, rate); in mt8186_mck_enable() local
544 int apll_clk_id = apll == MT8186_APLL1 ? in mt8186_mck_enable()
550 /* select apll */ in mt8186_mck_enable()
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| D | mt8186-dai-i2s.c | 43 int rate; /* for determine which apll to use */
508 /* apll */
586 /* which apll */ in mtk_afe_i2s_apll_connect()
588 /* choose APLL from i2s rate */ in mtk_afe_i2s_apll_connect()
627 /* which apll */ in mtk_afe_mclk_apll_connect()
1006 int apll; in mtk_dai_i2s_set_sysclk() local
1016 apll = mt8186_get_apll_by_rate(afe, freq); in mtk_dai_i2s_set_sysclk()
1017 apll_rate = mt8186_get_apll_rate(afe, apll); in mtk_dai_i2s_set_sysclk()
1020 dev_err(afe->dev, "%s(), freq > apll rate", __func__); in mtk_dai_i2s_set_sysclk()
1025 dev_err(afe->dev, "%s(), APLL cannot generate freq Hz", __func__); in mtk_dai_i2s_set_sysclk()
[all …]
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| /linux-6.12.1/drivers/clk/imx/ |
| D | clk-imx7ulp.c | 26 static const char * const apll_sels[] = { "apll", "apll_pfd_sel", };
34 /* used by sosc/sirc/firc/ddr/spll/apll dividers */
81 …hws[IMX7ULP_CLK_APLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "apll", "apll_pre_div", base + 0x500… in imx7ulp_clk_scg1_init()
84 /* APLL PFDs */ in imx7ulp_clk_scg1_init()
85 …hws[IMX7ULP_CLK_APLL_PFD0] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd0", "apll", base + 0x50c… in imx7ulp_clk_scg1_init()
86 …hws[IMX7ULP_CLK_APLL_PFD1] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd1", "apll", base + 0x50c… in imx7ulp_clk_scg1_init()
87 …hws[IMX7ULP_CLK_APLL_PFD2] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd2", "apll", base + 0x50c… in imx7ulp_clk_scg1_init()
88 …hws[IMX7ULP_CLK_APLL_PFD3] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd3", "apll", base + 0x50c… in imx7ulp_clk_scg1_init()
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| /linux-6.12.1/sound/soc/mediatek/mt8183/ |
| D | mt8183-afe-clk.c | 29 /* apll related mux */
230 /* apll */
384 /* setting for APLL */ in mt8183_apll1_enable()
438 /* setting for APLL */ in mt8183_apll2_enable()
487 int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll) in mt8183_get_apll_rate() argument
489 return (apll == MT8183_APLL1) ? 180633600 : 196608000; in mt8183_get_apll_rate()
545 int apll = mt8183_get_apll_by_rate(afe, rate); in mt8183_mck_enable() local
546 int apll_clk_id = apll == MT8183_APLL1 ? in mt8183_mck_enable()
556 /* select apll */ in mt8183_mck_enable()
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| D | mt8183-afe-clk.h | 12 /* APLL */
32 int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll);
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| D | mt8183-dai-i2s.c | 43 int rate; /* for determine which apll to use */
404 /* apll */
482 /* which apll */ in mtk_afe_i2s_apll_connect()
485 /* choose APLL from i2s rate */ in mtk_afe_i2s_apll_connect()
536 /* which apll */ in mtk_afe_mclk_apll_connect()
787 int apll; in mtk_dai_i2s_set_sysclk() local
800 apll = mt8183_get_apll_by_rate(afe, freq); in mtk_dai_i2s_set_sysclk()
801 apll_rate = mt8183_get_apll_rate(afe, apll); in mtk_dai_i2s_set_sysclk()
804 dev_warn(afe->dev, "%s(), freq > apll rate", __func__); in mtk_dai_i2s_set_sysclk()
809 dev_warn(afe->dev, "%s(), APLL cannot generate freq Hz", in mtk_dai_i2s_set_sysclk()
[all …]
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| D | mt8183-dai-tdm.c | 340 /* which apll */ in mtk_afe_tdm_apll_connect()
440 int apll; in mtk_dai_tdm_cal_mclk() local
443 apll = mt8183_get_apll_by_rate(afe, freq); in mtk_dai_tdm_cal_mclk()
444 apll_rate = mt8183_get_apll_rate(afe, apll); in mtk_dai_tdm_cal_mclk()
454 "%s(), APLL cannot generate %d Hz", __func__, freq); in mtk_dai_tdm_cal_mclk()
459 tdm_priv->mclk_apll = apll; in mtk_dai_tdm_cal_mclk()
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | imx7ulp-pcc-clock.yaml | 54 - description: apll pfd2
55 - description: apll pfd1
56 - description: apll pfd0
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| /linux-6.12.1/drivers/clk/nuvoton/ |
| D | clk-ma35d1.c | 89 { .fw_name = "apll", },
95 { .fw_name = "apll", },
294 { .fw_name = "apll", },
299 { .fw_name = "apll", },
304 { .fw_name = "apll", },
309 { .fw_name = "apll", },
314 { .fw_name = "apll", },
319 { .fw_name = "apll", },
323 { .fw_name = "apll", },
328 { .fw_name = "apll", },
[all …]
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| /linux-6.12.1/drivers/clk/rockchip/ |
| D | clk-rk3036.c | 21 apll, dpll, gpll, enumerator
117 PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
118 PNAME(mux_busclk_p) = { "apll", "dpll_cpu", "gpll_cpu" };
120 PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
123 PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
126 PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
137 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
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| D | clk-rv1108.c | 19 apll, dpll, gpll, enumerator
127 PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" };
147 PNAME(mux_dsp_src_p) = { "dpll", "gpll", "apll", "usb480m" };
151 PNAME(mux_cvbs_src_p) = { "apll", "io_cvbs_clkin", "hdmiphy", "gpll" };
154 [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0),
203 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
537 GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED,
666 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
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| D | clk-rk3188.c | 19 apll, cpll, dpll, gpll, enumerator
199 PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
203 PNAME(mux_aclk_cpu_p) = { "apll", "gpll" };
216 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
227 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
680 /* do not source aclk_cpu_pre from the apll, to keep complexity down */
843 /* reparent aclk_cpu_pre from apll */ in rk3188a_clk_init()
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| /linux-6.12.1/sound/soc/mediatek/mt8192/ |
| D | mt8192-afe-clk.c | 290 /* setting for APLL */ in mt8192_apll1_enable()
340 /* setting for APLL */ in mt8192_apll2_enable()
385 int mt8192_get_apll_rate(struct mtk_base_afe *afe, int apll) in mt8192_get_apll_rate() argument
387 return (apll == MT8192_APLL1) ? 180633600 : 196608000; in mt8192_get_apll_rate()
565 int apll = mt8192_get_apll_by_rate(afe, rate); in mt8192_mck_enable() local
566 int apll_clk_id = apll == MT8192_APLL1 ? in mt8192_mck_enable()
572 /* select apll */ in mt8192_mck_enable()
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| D | mt8192-afe-clk.h | 165 /* APLL */
186 /* apll related mux */
233 int mt8192_get_apll_rate(struct mtk_base_afe *afe, int apll);
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| D | mt8192-dai-tdm.c | 388 /* which apll */ in mtk_afe_tdm_apll_connect()
489 int apll; in mtk_dai_tdm_cal_mclk() local
492 apll = mt8192_get_apll_by_rate(afe, freq); in mtk_dai_tdm_cal_mclk()
493 apll_rate = mt8192_get_apll_rate(afe, apll); in mtk_dai_tdm_cal_mclk()
503 "%s(), APLL cannot generate %d Hz", __func__, freq); in mtk_dai_tdm_cal_mclk()
508 tdm_priv->mclk_apll = apll; in mtk_dai_tdm_cal_mclk()
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| /linux-6.12.1/sound/soc/mediatek/mt8188/ |
| D | mt8188-afe-clk.h | 14 /* APLL */
109 int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll);
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| D | mt8188-dai-etdm.c | 396 int apll; in mtk_dai_etdm_enable_mclk() local
403 apll = etdm_data->mclk_apll; in mtk_dai_etdm_enable_mclk()
404 apll_clk_id = mt8188_afe_get_mclk_source_clk_id(apll); in mtk_dai_etdm_enable_mclk()
421 /* enable parent clock before select apll*/ in mtk_dai_etdm_enable_mclk()
424 /* select apll */ in mtk_dai_etdm_enable_mclk()
1308 /* apll */
2238 int apll; in mtk_dai_etdm_cal_mclk() local
2250 apll = mt8188_afe_get_default_mclk_source_by_rate(freq); in mtk_dai_etdm_cal_mclk()
2252 apll = etdm_data->mclk_apll; in mtk_dai_etdm_cal_mclk()
2254 apll_rate = mt8188_afe_get_mclk_source_rate(afe, apll); in mtk_dai_etdm_cal_mclk()
[all …]
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| /linux-6.12.1/drivers/cpufreq/ |
| D | s5pv210-cpufreq.c | 87 /* APLL M,P,S values for 1G/800Mhz */
170 * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
286 * APLL should be changed in this level in s5pv210_target()
287 * APLL -> MPLL(for stable transition) -> APLL in s5pv210_target()
379 * 6. Turn on APLL in s5pv210_target()
422 /* 9. Change MPLL to APLL in MSYS_MUX */ in s5pv210_target()
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| /linux-6.12.1/drivers/clk/ti/ |
| D | apll.c | 3 * OMAP APLL clock support
200 pr_err("dra7 apll %pOFn must have parent(s)\n", node); in of_dra7_apll_setup()
230 CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
409 CLK_OF_DECLARE(omap2_apll_clock, "ti,omap2-apll-clock",
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| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | ti-phy.txt | 48 * "phy-div" - divider for apll
49 * "div-clk" - apll clock
|