1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Support for Medifield PNW Camera Imaging ISP subsystem.
4 *
5 * Copyright (c) 2010-2017 Intel Corporation. All Rights Reserved.
6 *
7 * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License version
11 * 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 *
19 */
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/pm_domain.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm_qos.h>
25 #include <linux/timer.h>
26 #include <linux/delay.h>
27 #include <linux/dmi.h>
28 #include <linux/interrupt.h>
29 #include <linux/bits.h>
30 #include <media/v4l2-fwnode.h>
31
32 #include <asm/iosf_mbi.h>
33
34 #include "../../include/linux/atomisp_gmin_platform.h"
35
36 #include "atomisp_cmd.h"
37 #include "atomisp_common.h"
38 #include "atomisp_fops.h"
39 #include "atomisp_ioctl.h"
40 #include "atomisp_internal.h"
41 #include "atomisp-regs.h"
42 #include "atomisp_dfs_tables.h"
43 #include "atomisp_drvfs.h"
44 #include "hmm/hmm.h"
45 #include "atomisp_trace_event.h"
46
47 #include "sh_css_firmware.h"
48
49 #include "device_access.h"
50
51 /* Timeouts to wait for all subdevs to be registered */
52 #define SUBDEV_WAIT_TIMEOUT 50 /* ms */
53 #define SUBDEV_WAIT_TIMEOUT_MAX_COUNT 40 /* up to 2 seconds */
54
55 /* G-Min addition: pull this in from intel_mid_pm.h */
56 #define CSTATE_EXIT_LATENCY_C1 1
57
58 /* cross componnet debug message flag */
59 int dbg_level;
60 module_param(dbg_level, int, 0644);
61 MODULE_PARM_DESC(dbg_level, "debug message level (default:0)");
62
63 /* log function switch */
64 int dbg_func = 1;
65 module_param(dbg_func, int, 0644);
66 MODULE_PARM_DESC(dbg_func,
67 "log function switch non/printk (default:printk)");
68
69 /*
70 * Set to 16x16 since this is the amount of lines and pixels the sensor
71 * exports extra. If these are kept at the 10x8 that they were on, in yuv
72 * downscaling modes incorrect resolutions where requested to the sensor
73 * driver with strange outcomes as a result. The proper way tot do this
74 * would be to have a list of tables the specify the sensor res, mipi rec,
75 * output res, and isp output res. however since we do not have this yet,
76 * the chosen solution is the next best thing.
77 */
78 int pad_w = 16;
79 module_param(pad_w, int, 0644);
80 MODULE_PARM_DESC(pad_w, "extra data for ISP processing");
81
82 int pad_h = 16;
83 module_param(pad_h, int, 0644);
84 MODULE_PARM_DESC(pad_h, "extra data for ISP processing");
85
86 /*
87 * FIXME: this is a hack to make easier to support ISP2401 variant.
88 * As a given system will either be ISP2401 or not, we can just use
89 * a boolean, in order to replace existing #ifdef ISP2401 everywhere.
90 *
91 * Once this driver gets into a better shape, however, the best would
92 * be to replace this to something stored inside atomisp allocated
93 * structures.
94 */
95
96 struct device *atomisp_dev;
97
98 static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = {
99 {
100 .width = ISP_FREQ_RULE_ANY,
101 .height = ISP_FREQ_RULE_ANY,
102 .fps = ISP_FREQ_RULE_ANY,
103 .isp_freq = ISP_FREQ_400MHZ,
104 .run_mode = ATOMISP_RUN_MODE_VIDEO,
105 },
106 {
107 .width = ISP_FREQ_RULE_ANY,
108 .height = ISP_FREQ_RULE_ANY,
109 .fps = ISP_FREQ_RULE_ANY,
110 .isp_freq = ISP_FREQ_400MHZ,
111 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
112 },
113 {
114 .width = ISP_FREQ_RULE_ANY,
115 .height = ISP_FREQ_RULE_ANY,
116 .fps = ISP_FREQ_RULE_ANY,
117 .isp_freq = ISP_FREQ_400MHZ,
118 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
119 },
120 };
121
122 /* Merrifield and Moorefield DFS rules */
123 static const struct atomisp_dfs_config dfs_config_merr = {
124 .lowest_freq = ISP_FREQ_200MHZ,
125 .max_freq_at_vmin = ISP_FREQ_400MHZ,
126 .highest_freq = ISP_FREQ_457MHZ,
127 .dfs_table = dfs_rules_merr,
128 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr),
129 };
130
131 static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = {
132 {
133 .width = ISP_FREQ_RULE_ANY,
134 .height = ISP_FREQ_RULE_ANY,
135 .fps = ISP_FREQ_RULE_ANY,
136 .isp_freq = ISP_FREQ_400MHZ,
137 .run_mode = ATOMISP_RUN_MODE_VIDEO,
138 },
139 {
140 .width = ISP_FREQ_RULE_ANY,
141 .height = ISP_FREQ_RULE_ANY,
142 .fps = ISP_FREQ_RULE_ANY,
143 .isp_freq = ISP_FREQ_400MHZ,
144 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
145 },
146 {
147 .width = ISP_FREQ_RULE_ANY,
148 .height = ISP_FREQ_RULE_ANY,
149 .fps = ISP_FREQ_RULE_ANY,
150 .isp_freq = ISP_FREQ_400MHZ,
151 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
152 },
153 };
154
155 static const struct atomisp_dfs_config dfs_config_merr_1179 = {
156 .lowest_freq = ISP_FREQ_200MHZ,
157 .max_freq_at_vmin = ISP_FREQ_400MHZ,
158 .highest_freq = ISP_FREQ_400MHZ,
159 .dfs_table = dfs_rules_merr_1179,
160 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179),
161 };
162
163 static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = {
164 {
165 .width = 1920,
166 .height = 1080,
167 .fps = 30,
168 .isp_freq = ISP_FREQ_266MHZ,
169 .run_mode = ATOMISP_RUN_MODE_VIDEO,
170 },
171 {
172 .width = 1080,
173 .height = 1920,
174 .fps = 30,
175 .isp_freq = ISP_FREQ_266MHZ,
176 .run_mode = ATOMISP_RUN_MODE_VIDEO,
177 },
178 {
179 .width = 1920,
180 .height = 1080,
181 .fps = 45,
182 .isp_freq = ISP_FREQ_320MHZ,
183 .run_mode = ATOMISP_RUN_MODE_VIDEO,
184 },
185 {
186 .width = 1080,
187 .height = 1920,
188 .fps = 45,
189 .isp_freq = ISP_FREQ_320MHZ,
190 .run_mode = ATOMISP_RUN_MODE_VIDEO,
191 },
192 {
193 .width = ISP_FREQ_RULE_ANY,
194 .height = ISP_FREQ_RULE_ANY,
195 .fps = 60,
196 .isp_freq = ISP_FREQ_356MHZ,
197 .run_mode = ATOMISP_RUN_MODE_VIDEO,
198 },
199 {
200 .width = ISP_FREQ_RULE_ANY,
201 .height = ISP_FREQ_RULE_ANY,
202 .fps = ISP_FREQ_RULE_ANY,
203 .isp_freq = ISP_FREQ_200MHZ,
204 .run_mode = ATOMISP_RUN_MODE_VIDEO,
205 },
206 {
207 .width = ISP_FREQ_RULE_ANY,
208 .height = ISP_FREQ_RULE_ANY,
209 .fps = ISP_FREQ_RULE_ANY,
210 .isp_freq = ISP_FREQ_400MHZ,
211 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
212 },
213 {
214 .width = ISP_FREQ_RULE_ANY,
215 .height = ISP_FREQ_RULE_ANY,
216 .fps = ISP_FREQ_RULE_ANY,
217 .isp_freq = ISP_FREQ_200MHZ,
218 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
219 },
220 };
221
222 static struct atomisp_dfs_config dfs_config_merr_117a = {
223 .lowest_freq = ISP_FREQ_200MHZ,
224 .max_freq_at_vmin = ISP_FREQ_200MHZ,
225 .highest_freq = ISP_FREQ_400MHZ,
226 .dfs_table = dfs_rules_merr_117a,
227 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a),
228 };
229
230 static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = {
231 {
232 .width = ISP_FREQ_RULE_ANY,
233 .height = ISP_FREQ_RULE_ANY,
234 .fps = ISP_FREQ_RULE_ANY,
235 .isp_freq = ISP_FREQ_400MHZ,
236 .run_mode = ATOMISP_RUN_MODE_VIDEO,
237 },
238 {
239 .width = ISP_FREQ_RULE_ANY,
240 .height = ISP_FREQ_RULE_ANY,
241 .fps = ISP_FREQ_RULE_ANY,
242 .isp_freq = ISP_FREQ_400MHZ,
243 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
244 },
245 {
246 .width = ISP_FREQ_RULE_ANY,
247 .height = ISP_FREQ_RULE_ANY,
248 .fps = ISP_FREQ_RULE_ANY,
249 .isp_freq = ISP_FREQ_400MHZ,
250 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
251 },
252 };
253
254 static const struct atomisp_dfs_config dfs_config_byt = {
255 .lowest_freq = ISP_FREQ_200MHZ,
256 .max_freq_at_vmin = ISP_FREQ_400MHZ,
257 .highest_freq = ISP_FREQ_400MHZ,
258 .dfs_table = dfs_rules_byt,
259 .dfs_table_size = ARRAY_SIZE(dfs_rules_byt),
260 };
261
262 static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = {
263 {
264 .width = ISP_FREQ_RULE_ANY,
265 .height = ISP_FREQ_RULE_ANY,
266 .fps = ISP_FREQ_RULE_ANY,
267 .isp_freq = ISP_FREQ_320MHZ,
268 .run_mode = ATOMISP_RUN_MODE_VIDEO,
269 },
270 {
271 .width = ISP_FREQ_RULE_ANY,
272 .height = ISP_FREQ_RULE_ANY,
273 .fps = ISP_FREQ_RULE_ANY,
274 .isp_freq = ISP_FREQ_356MHZ,
275 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
276 },
277 {
278 .width = ISP_FREQ_RULE_ANY,
279 .height = ISP_FREQ_RULE_ANY,
280 .fps = ISP_FREQ_RULE_ANY,
281 .isp_freq = ISP_FREQ_320MHZ,
282 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
283 },
284 };
285
286 static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = {
287 {
288 .width = ISP_FREQ_RULE_ANY,
289 .height = ISP_FREQ_RULE_ANY,
290 .fps = ISP_FREQ_RULE_ANY,
291 .isp_freq = ISP_FREQ_356MHZ,
292 .run_mode = ATOMISP_RUN_MODE_VIDEO,
293 },
294 {
295 .width = ISP_FREQ_RULE_ANY,
296 .height = ISP_FREQ_RULE_ANY,
297 .fps = ISP_FREQ_RULE_ANY,
298 .isp_freq = ISP_FREQ_356MHZ,
299 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
300 },
301 {
302 .width = ISP_FREQ_RULE_ANY,
303 .height = ISP_FREQ_RULE_ANY,
304 .fps = ISP_FREQ_RULE_ANY,
305 .isp_freq = ISP_FREQ_320MHZ,
306 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
307 },
308 };
309
310 static const struct atomisp_dfs_config dfs_config_cht = {
311 .lowest_freq = ISP_FREQ_100MHZ,
312 .max_freq_at_vmin = ISP_FREQ_356MHZ,
313 .highest_freq = ISP_FREQ_356MHZ,
314 .dfs_table = dfs_rules_cht,
315 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht),
316 };
317
318 /* This one should be visible also by atomisp_cmd.c */
319 const struct atomisp_dfs_config dfs_config_cht_soc = {
320 .lowest_freq = ISP_FREQ_100MHZ,
321 .max_freq_at_vmin = ISP_FREQ_356MHZ,
322 .highest_freq = ISP_FREQ_356MHZ,
323 .dfs_table = dfs_rules_cht_soc,
324 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc),
325 };
326
atomisp_video_init(struct atomisp_video_pipe * video)327 int atomisp_video_init(struct atomisp_video_pipe *video)
328 {
329 int ret;
330
331 video->pad.flags = MEDIA_PAD_FL_SINK;
332 ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad);
333 if (ret < 0)
334 return ret;
335
336 /* Initialize the video device. */
337 strscpy(video->vdev.name, "ATOMISP video output", sizeof(video->vdev.name));
338 video->vdev.fops = &atomisp_fops;
339 video->vdev.ioctl_ops = &atomisp_ioctl_ops;
340 video->vdev.lock = &video->isp->mutex;
341 video->vdev.release = video_device_release_empty;
342 video_set_drvdata(&video->vdev, video->isp);
343
344 return 0;
345 }
346
atomisp_video_unregister(struct atomisp_video_pipe * video)347 void atomisp_video_unregister(struct atomisp_video_pipe *video)
348 {
349 if (video_is_registered(&video->vdev)) {
350 media_entity_cleanup(&video->vdev.entity);
351 video_unregister_device(&video->vdev);
352 }
353 }
354
atomisp_save_iunit_reg(struct atomisp_device * isp)355 static int atomisp_save_iunit_reg(struct atomisp_device *isp)
356 {
357 struct pci_dev *pdev = to_pci_dev(isp->dev);
358
359 dev_dbg(isp->dev, "%s\n", __func__);
360
361 pci_read_config_word(pdev, PCI_COMMAND, &isp->saved_regs.pcicmdsts);
362 /* isp->saved_regs.ispmmadr is set from the atomisp_pci_probe() */
363 pci_read_config_dword(pdev, PCI_MSI_CAPID, &isp->saved_regs.msicap);
364 pci_read_config_dword(pdev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr);
365 pci_read_config_word(pdev, PCI_MSI_DATA, &isp->saved_regs.msi_data);
366 pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr);
367 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &isp->saved_regs.interrupt_control);
368
369 pci_read_config_dword(pdev, MRFLD_PCI_PMCS, &isp->saved_regs.pmcs);
370 /* Ensure read/write combining is enabled. */
371 pci_read_config_dword(pdev, PCI_I_CONTROL, &isp->saved_regs.i_control);
372 isp->saved_regs.i_control |=
373 MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING |
374 MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING;
375 pci_read_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
376 &isp->saved_regs.csi_access_viol);
377 pci_read_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
378 &isp->saved_regs.csi_rcomp_config);
379 /*
380 * Hardware bugs require setting CSI_HS_OVR_CLK_GATE_ON_UPDATE.
381 * ANN/CHV: RCOMP updates do not happen when using CSI2+ path
382 * and sensor sending "continuous clock".
383 * TNG/ANN/CHV: MIPI packets are lost if the HS entry sequence
384 * is missed, and IUNIT can hang.
385 * For both issues, setting this bit is a workaround.
386 */
387 isp->saved_regs.csi_rcomp_config |= MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE;
388 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
389 &isp->saved_regs.csi_afe_dly);
390 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
391 &isp->saved_regs.csi_control);
392 if (isp->media_dev.hw_revision >=
393 (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT))
394 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_PARPATHEN;
395 /*
396 * On CHT CSI_READY bit should be enabled before stream on
397 */
398 if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 <<
399 ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)))
400 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_CSI_READY;
401 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
402 &isp->saved_regs.csi_afe_rcomp_config);
403 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
404 &isp->saved_regs.csi_afe_hs_control);
405 pci_read_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
406 &isp->saved_regs.csi_deadline_control);
407 return 0;
408 }
409
atomisp_restore_iunit_reg(struct atomisp_device * isp)410 static int atomisp_restore_iunit_reg(struct atomisp_device *isp)
411 {
412 struct pci_dev *pdev = to_pci_dev(isp->dev);
413
414 dev_dbg(isp->dev, "%s\n", __func__);
415
416 pci_write_config_word(pdev, PCI_COMMAND, isp->saved_regs.pcicmdsts);
417 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, isp->saved_regs.ispmmadr);
418 pci_write_config_dword(pdev, PCI_MSI_CAPID, isp->saved_regs.msicap);
419 pci_write_config_dword(pdev, PCI_MSI_ADDR, isp->saved_regs.msi_addr);
420 pci_write_config_word(pdev, PCI_MSI_DATA, isp->saved_regs.msi_data);
421 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, isp->saved_regs.intr);
422 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, isp->saved_regs.interrupt_control);
423 pci_write_config_dword(pdev, PCI_I_CONTROL, isp->saved_regs.i_control);
424
425 pci_write_config_dword(pdev, MRFLD_PCI_PMCS, isp->saved_regs.pmcs);
426 pci_write_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
427 isp->saved_regs.csi_access_viol);
428 pci_write_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
429 isp->saved_regs.csi_rcomp_config);
430 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
431 isp->saved_regs.csi_afe_dly);
432 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
433 isp->saved_regs.csi_control);
434 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
435 isp->saved_regs.csi_afe_rcomp_config);
436 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
437 isp->saved_regs.csi_afe_hs_control);
438 pci_write_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
439 isp->saved_regs.csi_deadline_control);
440
441 /*
442 * for MRFLD, Software/firmware needs to write a 1 to bit0
443 * of the register at CSI_RECEIVER_SELECTION_REG to enable
444 * SH CSI backend write 0 will enable Arasan CSI backend,
445 * which has bugs(like sighting:4567697 and 4567699) and
446 * will be removed in B0
447 */
448 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
449 return 0;
450 }
451
atomisp_mrfld_pre_power_down(struct atomisp_device * isp)452 static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp)
453 {
454 struct pci_dev *pdev = to_pci_dev(isp->dev);
455 u32 irq;
456 unsigned long flags;
457
458 spin_lock_irqsave(&isp->lock, flags);
459
460 /*
461 * MRFLD HAS requirement: cannot power off i-unit if
462 * ISP has IRQ not serviced.
463 * So, here we need to check if there is any pending
464 * IRQ, if so, waiting for it to be served
465 */
466 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
467 irq &= BIT(INTR_IIR);
468 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
469
470 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
471 if (!(irq & BIT(INTR_IIR)))
472 goto done;
473
474 atomisp_css2_hw_store_32(MRFLD_INTR_CLEAR_REG, 0xFFFFFFFF);
475 atomisp_load_uint32(MRFLD_INTR_STATUS_REG, &irq);
476 if (irq != 0) {
477 dev_err(isp->dev,
478 "%s: fail to clear isp interrupt status reg=0x%x\n",
479 __func__, irq);
480 spin_unlock_irqrestore(&isp->lock, flags);
481 return -EAGAIN;
482 } else {
483 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
484 irq &= BIT(INTR_IIR);
485 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
486
487 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
488 if (!(irq & BIT(INTR_IIR))) {
489 atomisp_css2_hw_store_32(MRFLD_INTR_ENABLE_REG, 0x0);
490 goto done;
491 }
492 dev_err(isp->dev,
493 "%s: error in iunit interrupt. status reg=0x%x\n",
494 __func__, irq);
495 spin_unlock_irqrestore(&isp->lock, flags);
496 return -EAGAIN;
497 }
498 done:
499 /*
500 * MRFLD WORKAROUND:
501 * before powering off IUNIT, clear the pending interrupts
502 * and disable the interrupt. driver should avoid writing 0
503 * to IIR. It could block subsequent interrupt messages.
504 * HW sighting:4568410.
505 */
506 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
507 irq &= ~BIT(INTR_IER);
508 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
509
510 atomisp_msi_irq_uninit(isp);
511 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
512 spin_unlock_irqrestore(&isp->lock, flags);
513
514 return 0;
515 }
516
517 /*
518 * WA for DDR DVFS enable/disable
519 * By default, ISP will force DDR DVFS 1600MHz before disable DVFS
520 */
punit_ddr_dvfs_enable(bool enable)521 static void punit_ddr_dvfs_enable(bool enable)
522 {
523 int reg;
524
525 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®);
526 if (enable) {
527 reg &= ~(MRFLD_BIT0 | MRFLD_BIT1);
528 } else {
529 reg |= MRFLD_BIT1;
530 reg &= ~(MRFLD_BIT0);
531 }
532 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, MRFLD_ISPSSDVFS, reg);
533 }
534
atomisp_mrfld_power(struct atomisp_device * isp,bool enable)535 static int atomisp_mrfld_power(struct atomisp_device *isp, bool enable)
536 {
537 struct pci_dev *pdev = to_pci_dev(isp->dev);
538 unsigned long timeout;
539 u32 val = enable ? MRFLD_ISPSSPM0_IUNIT_POWER_ON :
540 MRFLD_ISPSSPM0_IUNIT_POWER_OFF;
541
542 dev_dbg(isp->dev, "IUNIT power-%s.\n", enable ? "on" : "off");
543
544 /* WA for P-Unit, if DVFS enabled, ISP timeout observed */
545 if (IS_CHT && enable && !isp->pm_only) {
546 punit_ddr_dvfs_enable(false);
547 msleep(20);
548 }
549
550 /* Write to ISPSSPM0 bit[1:0] to power on/off the IUNIT */
551 iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0,
552 val, MRFLD_ISPSSPM0_ISPSSC_MASK);
553
554 /* WA:Enable DVFS */
555 if (IS_CHT && !enable && !isp->pm_only)
556 punit_ddr_dvfs_enable(true);
557
558 /*
559 * There should be no IUNIT access while power-down is
560 * in progress. HW sighting: 4567865.
561 * Wait up to 50 ms for the IUNIT to shut down.
562 * And we do the same for power on.
563 */
564 timeout = jiffies + msecs_to_jiffies(50);
565 do {
566 u32 tmp;
567
568 /* Wait until ISPSSPM0 bit[25:24] shows the right value */
569 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, &tmp);
570 tmp = (tmp >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) & MRFLD_ISPSSPM0_ISPSSC_MASK;
571 if (tmp == val) {
572 trace_ipu_cstate(enable);
573 pdev->current_state = enable ? PCI_D0 : PCI_D3cold;
574 return 0;
575 }
576
577 if (time_after(jiffies, timeout))
578 break;
579
580 /* FIXME: experienced value for delay */
581 usleep_range(100, 150);
582 } while (1);
583
584 dev_err(isp->dev, "IUNIT power-%s timeout.\n", enable ? "on" : "off");
585 return -EBUSY;
586 }
587
atomisp_power_off(struct device * dev)588 int atomisp_power_off(struct device *dev)
589 {
590 struct atomisp_device *isp = dev_get_drvdata(dev);
591 struct pci_dev *pdev = to_pci_dev(dev);
592 int ret;
593 u32 reg;
594
595 if (isp->pm_only) {
596 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, 0);
597 } else {
598 atomisp_css_uninit(isp);
599
600 ret = atomisp_mrfld_pre_power_down(isp);
601 if (ret)
602 return ret;
603 }
604
605 /*
606 * MRFLD IUNIT DPHY is located in an always-power-on island
607 * MRFLD HW design need all CSI ports are disabled before
608 * powering down the IUNIT.
609 */
610 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, ®);
611 reg |= MRFLD_ALL_CSI_PORTS_OFF_MASK;
612 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, reg);
613
614 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
615 pci_save_state(pdev);
616 return atomisp_mrfld_power(isp, false);
617 }
618
atomisp_power_on(struct device * dev)619 int atomisp_power_on(struct device *dev)
620 {
621 struct atomisp_device *isp = (struct atomisp_device *)
622 dev_get_drvdata(dev);
623 int ret;
624
625 ret = atomisp_mrfld_power(isp, true);
626 if (ret)
627 return ret;
628
629 pci_restore_state(to_pci_dev(dev));
630 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency);
631
632 if (isp->pm_only)
633 return 0;
634
635 /*restore register values for iUnit and iUnitPHY registers*/
636 if (isp->saved_regs.pcicmdsts)
637 atomisp_restore_iunit_reg(isp);
638
639 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
640
641 return atomisp_css_init(isp);
642 }
643
atomisp_suspend(struct device * dev)644 static int atomisp_suspend(struct device *dev)
645 {
646 struct atomisp_device *isp = (struct atomisp_device *)
647 dev_get_drvdata(dev);
648 unsigned long flags;
649
650 /* FIXME: Suspend is not supported by sensors. Abort if streaming. */
651 spin_lock_irqsave(&isp->lock, flags);
652 if (isp->asd.streaming) {
653 spin_unlock_irqrestore(&isp->lock, flags);
654 dev_err(isp->dev, "atomisp cannot suspend at this time.\n");
655 return -EINVAL;
656 }
657 spin_unlock_irqrestore(&isp->lock, flags);
658
659 pm_runtime_resume(dev);
660
661 isp->asd.recreate_streams_on_resume = isp->asd.stream_prepared;
662 atomisp_destroy_pipes_stream(&isp->asd);
663
664 return atomisp_power_off(dev);
665 }
666
atomisp_resume(struct device * dev)667 static int atomisp_resume(struct device *dev)
668 {
669 struct atomisp_device *isp = dev_get_drvdata(dev);
670 int ret;
671
672 ret = atomisp_power_on(dev);
673 if (ret)
674 return ret;
675
676 if (isp->asd.recreate_streams_on_resume)
677 ret = atomisp_create_pipes_stream(&isp->asd);
678
679 return ret;
680 }
681
atomisp_csi_lane_config(struct atomisp_device * isp)682 int atomisp_csi_lane_config(struct atomisp_device *isp)
683 {
684 struct pci_dev *pdev = to_pci_dev(isp->dev);
685 static const struct {
686 u8 code;
687 u8 lanes[N_MIPI_PORT_ID];
688 } portconfigs[] = {
689 /* Tangier/Merrifield available lane configurations */
690 { 0x00, { 4, 1, 0 } }, /* 00000 */
691 { 0x01, { 3, 1, 0 } }, /* 00001 */
692 { 0x02, { 2, 1, 0 } }, /* 00010 */
693 { 0x03, { 1, 1, 0 } }, /* 00011 */
694 { 0x04, { 2, 1, 2 } }, /* 00100 */
695 { 0x08, { 3, 1, 1 } }, /* 01000 */
696 { 0x09, { 2, 1, 1 } }, /* 01001 */
697 { 0x0a, { 1, 1, 1 } }, /* 01010 */
698
699 /* Anniedale/Moorefield only configurations */
700 { 0x10, { 4, 2, 0 } }, /* 10000 */
701 { 0x11, { 3, 2, 0 } }, /* 10001 */
702 { 0x12, { 2, 2, 0 } }, /* 10010 */
703 { 0x13, { 1, 2, 0 } }, /* 10011 */
704 { 0x14, { 2, 2, 2 } }, /* 10100 */
705 { 0x18, { 3, 2, 1 } }, /* 11000 */
706 { 0x19, { 2, 2, 1 } }, /* 11001 */
707 { 0x1a, { 1, 2, 1 } }, /* 11010 */
708 };
709
710 unsigned int i, j;
711 u32 csi_control;
712 int nportconfigs;
713 u32 port_config_mask;
714 int port3_lanes_shift;
715
716 if (isp->media_dev.hw_revision <
717 ATOMISP_HW_REVISION_ISP2401_LEGACY <<
718 ATOMISP_HW_REVISION_SHIFT) {
719 /* Merrifield */
720 port_config_mask = MRFLD_PORT_CONFIG_MASK;
721 port3_lanes_shift = MRFLD_PORT3_LANES_SHIFT;
722 } else {
723 /* Moorefield / Cherryview */
724 port_config_mask = CHV_PORT_CONFIG_MASK;
725 port3_lanes_shift = CHV_PORT3_LANES_SHIFT;
726 }
727
728 if (isp->media_dev.hw_revision <
729 ATOMISP_HW_REVISION_ISP2401 <<
730 ATOMISP_HW_REVISION_SHIFT) {
731 /* Merrifield / Moorefield legacy input system */
732 nportconfigs = MRFLD_PORT_CONFIG_NUM;
733 } else {
734 /* Moorefield / Cherryview new input system */
735 nportconfigs = ARRAY_SIZE(portconfigs);
736 }
737
738 for (i = 0; i < nportconfigs; i++) {
739 for (j = 0; j < N_MIPI_PORT_ID; j++)
740 if (isp->sensor_lanes[j] &&
741 isp->sensor_lanes[j] != portconfigs[i].lanes[j])
742 break;
743
744 if (j == N_MIPI_PORT_ID)
745 break; /* Found matching setting */
746 }
747
748 if (i >= nportconfigs) {
749 dev_err(isp->dev,
750 "%s: could not find the CSI port setting for %d-%d-%d\n",
751 __func__,
752 isp->sensor_lanes[0], isp->sensor_lanes[1], isp->sensor_lanes[2]);
753 return -EINVAL;
754 }
755
756 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, &csi_control);
757 csi_control &= ~port_config_mask;
758 csi_control |= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT)
759 | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT))
760 | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT))
761 | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT))
762 | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT)
763 | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT)
764 | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift);
765
766 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, csi_control);
767
768 dev_dbg(isp->dev,
769 "%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n",
770 __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[1],
771 portconfigs[i].lanes[2], csi_control);
772
773 return 0;
774 }
775
atomisp_subdev_probe(struct atomisp_device * isp)776 static int atomisp_subdev_probe(struct atomisp_device *isp)
777 {
778 const struct intel_v4l2_subdev_table *subdevs;
779 int ret, mipi_port;
780
781 ret = atomisp_csi2_bridge_parse_firmware(isp);
782 if (ret)
783 return ret;
784
785 /*
786 * TODO: this is left here for now to allow testing atomisp-sensor
787 * drivers which are still using the atomisp_gmin_platform infra before
788 * converting them to standard v4l2 sensor drivers using runtime-pm +
789 * ACPI for pm and v4l2_async_register_subdev_sensor() registration.
790 */
791 for (subdevs = atomisp_platform_get_subdevs(); subdevs->subdev; subdevs++) {
792 ret = v4l2_device_register_subdev(&isp->v4l2_dev, subdevs->subdev);
793 if (ret)
794 continue;
795
796 if (subdevs->port >= ATOMISP_CAMERA_NR_PORTS) {
797 dev_err(isp->dev, "port %d not supported\n", subdevs->port);
798 continue;
799 }
800
801 if (isp->sensor_subdevs[subdevs->port]) {
802 dev_err(isp->dev, "port %d already has a sensor attached\n",
803 subdevs->port);
804 continue;
805 }
806
807 mipi_port = atomisp_port_to_mipi_port(isp, subdevs->port);
808 isp->sensor_lanes[mipi_port] = subdevs->lanes;
809 isp->sensor_subdevs[subdevs->port] = subdevs->subdev;
810 }
811
812 return atomisp_csi_lane_config(isp);
813 }
814
atomisp_unregister_entities(struct atomisp_device * isp)815 static void atomisp_unregister_entities(struct atomisp_device *isp)
816 {
817 unsigned int i;
818 struct v4l2_subdev *sd, *next;
819
820 atomisp_subdev_unregister_entities(&isp->asd);
821 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
822 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
823
824 list_for_each_entry_safe(sd, next, &isp->v4l2_dev.subdevs, list)
825 v4l2_device_unregister_subdev(sd);
826
827 v4l2_device_unregister(&isp->v4l2_dev);
828 media_device_unregister(&isp->media_dev);
829 media_device_cleanup(&isp->media_dev);
830
831 for (i = 0; i < isp->input_cnt; i++)
832 __v4l2_subdev_state_free(isp->inputs[i].try_sd_state);
833 }
834
atomisp_register_entities(struct atomisp_device * isp)835 static int atomisp_register_entities(struct atomisp_device *isp)
836 {
837 int ret = 0;
838 unsigned int i;
839
840 isp->media_dev.dev = isp->dev;
841
842 strscpy(isp->media_dev.model, "Intel Atom ISP",
843 sizeof(isp->media_dev.model));
844
845 media_device_init(&isp->media_dev);
846 isp->v4l2_dev.mdev = &isp->media_dev;
847 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
848 if (ret < 0) {
849 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
850 __func__, ret);
851 goto v4l2_device_failed;
852 }
853
854 ret = atomisp_subdev_probe(isp);
855 if (ret < 0)
856 goto csi_and_subdev_probe_failed;
857
858 /* Register internal entities */
859 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
860 ret = atomisp_mipi_csi2_register_entities(&isp->csi2_port[i],
861 &isp->v4l2_dev);
862 if (ret == 0)
863 continue;
864
865 /* error case */
866 dev_err(isp->dev, "failed to register the CSI port: %d\n", i);
867 /* deregister all registered CSI ports */
868 while (i--)
869 atomisp_mipi_csi2_unregister_entities(
870 &isp->csi2_port[i]);
871
872 goto csi_and_subdev_probe_failed;
873 }
874
875 ret = atomisp_subdev_register_subdev(&isp->asd, &isp->v4l2_dev);
876 if (ret < 0) {
877 dev_err(isp->dev, "atomisp_subdev_register_subdev fail\n");
878 goto subdev_register_failed;
879 }
880
881 return 0;
882
883 subdev_register_failed:
884 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
885 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
886 csi_and_subdev_probe_failed:
887 v4l2_device_unregister(&isp->v4l2_dev);
888 v4l2_device_failed:
889 media_device_unregister(&isp->media_dev);
890 media_device_cleanup(&isp->media_dev);
891 return ret;
892 }
893
atomisp_init_sensor(struct atomisp_input_subdev * input)894 static void atomisp_init_sensor(struct atomisp_input_subdev *input)
895 {
896 static struct lock_class_key try_sd_state_key;
897 struct v4l2_subdev_mbus_code_enum mbus_code_enum = { };
898 struct v4l2_subdev_frame_size_enum fse = { };
899 struct v4l2_subdev_selection sel = { };
900 struct v4l2_subdev_state *try_sd_state, *act_sd_state;
901 int i, err;
902
903 /*
904 * FIXME: Drivers are not supposed to use __v4l2_subdev_state_alloc()
905 * but atomisp needs this for try_fmt on its /dev/video# node since
906 * it emulates a normal v4l2 device there, passing through try_fmt /
907 * set_fmt to the sensor.
908 */
909 try_sd_state = __v4l2_subdev_state_alloc(input->camera,
910 "atomisp:try_sd_state->lock", &try_sd_state_key);
911 if (IS_ERR(try_sd_state))
912 return;
913
914 input->try_sd_state = try_sd_state;
915
916 act_sd_state = v4l2_subdev_lock_and_get_active_state(input->camera);
917
918 mbus_code_enum.which = V4L2_SUBDEV_FORMAT_ACTIVE;
919 err = v4l2_subdev_call(input->camera, pad, enum_mbus_code,
920 act_sd_state, &mbus_code_enum);
921 if (!err)
922 input->code = mbus_code_enum.code;
923
924 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
925 sel.target = V4L2_SEL_TGT_NATIVE_SIZE;
926 err = v4l2_subdev_call(input->camera, pad, get_selection,
927 act_sd_state, &sel);
928 if (err)
929 goto unlock_act_sd_state;
930
931 input->native_rect = sel.r;
932
933 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
934 sel.target = V4L2_SEL_TGT_CROP_DEFAULT;
935 err = v4l2_subdev_call(input->camera, pad, get_selection,
936 act_sd_state, &sel);
937 if (err)
938 goto unlock_act_sd_state;
939
940 input->active_rect = sel.r;
941
942 /*
943 * Check for a framesize with half active_rect width and height,
944 * if found assume the sensor supports binning.
945 * Do this before changing the crop-rect since that may influence
946 * enum_frame_size results.
947 */
948 for (i = 0; ; i++) {
949 fse.index = i;
950 fse.code = input->code;
951 fse.which = V4L2_SUBDEV_FORMAT_ACTIVE;
952
953 err = v4l2_subdev_call(input->camera, pad, enum_frame_size,
954 act_sd_state, &fse);
955 if (err)
956 break;
957
958 if (fse.min_width <= (input->active_rect.width / 2) &&
959 fse.min_height <= (input->active_rect.height / 2)) {
960 input->binning_support = true;
961 break;
962 }
963 }
964
965 /*
966 * The ISP also wants the non-active pixels at the border of the sensor
967 * for padding, set the crop rect to cover the entire sensor instead
968 * of only the default active area.
969 *
970 * Do this for both try and active formats since the crop rect in
971 * try_sd_state may influence (clamp size) in calls with which == try.
972 */
973 sel.which = V4L2_SUBDEV_FORMAT_TRY;
974 sel.target = V4L2_SEL_TGT_CROP;
975 sel.r = input->native_rect;
976 v4l2_subdev_lock_state(input->try_sd_state);
977 err = v4l2_subdev_call(input->camera, pad, set_selection,
978 input->try_sd_state, &sel);
979 v4l2_subdev_unlock_state(input->try_sd_state);
980 if (err)
981 goto unlock_act_sd_state;
982
983 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
984 sel.target = V4L2_SEL_TGT_CROP;
985 sel.r = input->native_rect;
986 err = v4l2_subdev_call(input->camera, pad, set_selection,
987 act_sd_state, &sel);
988 if (err)
989 goto unlock_act_sd_state;
990
991 dev_info(input->camera->dev, "Supports crop native %dx%d active %dx%d binning %d\n",
992 input->native_rect.width, input->native_rect.height,
993 input->active_rect.width, input->active_rect.height,
994 input->binning_support);
995
996 input->crop_support = true;
997
998 unlock_act_sd_state:
999 if (act_sd_state)
1000 v4l2_subdev_unlock_state(act_sd_state);
1001 }
1002
atomisp_register_device_nodes(struct atomisp_device * isp)1003 int atomisp_register_device_nodes(struct atomisp_device *isp)
1004 {
1005 struct atomisp_input_subdev *input;
1006 int i, err;
1007
1008 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
1009 err = media_create_pad_link(&isp->csi2_port[i].subdev.entity,
1010 CSI2_PAD_SOURCE, &isp->asd.subdev.entity,
1011 ATOMISP_SUBDEV_PAD_SINK, 0);
1012 if (err)
1013 return err;
1014
1015 if (!isp->sensor_subdevs[i])
1016 continue;
1017
1018 input = &isp->inputs[isp->input_cnt];
1019
1020 input->port = i;
1021 input->camera = isp->sensor_subdevs[i];
1022 input->csi_port = &isp->csi2_port[i].subdev;
1023
1024 atomisp_init_sensor(input);
1025
1026 err = media_create_pad_link(&input->camera->entity, 0,
1027 &isp->csi2_port[i].subdev.entity,
1028 CSI2_PAD_SINK,
1029 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1030 if (err)
1031 return err;
1032
1033 isp->input_cnt++;
1034 }
1035
1036 if (!isp->input_cnt)
1037 dev_warn(isp->dev, "no camera attached or fail to detect\n");
1038 else
1039 dev_info(isp->dev, "detected %d camera sensors\n", isp->input_cnt);
1040
1041 mutex_lock(&isp->media_dev.graph_mutex);
1042 atomisp_setup_input_links(isp);
1043 mutex_unlock(&isp->media_dev.graph_mutex);
1044
1045 isp->asd.video_out.vdev.v4l2_dev = &isp->v4l2_dev;
1046 isp->asd.video_out.vdev.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1047 err = video_register_device(&isp->asd.video_out.vdev, VFL_TYPE_VIDEO, -1);
1048 if (err)
1049 return err;
1050
1051 err = media_create_pad_link(&isp->asd.subdev.entity, ATOMISP_SUBDEV_PAD_SOURCE,
1052 &isp->asd.video_out.vdev.entity, 0,
1053 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1054 if (err)
1055 return err;
1056
1057 err = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
1058 if (err)
1059 return err;
1060
1061 return media_device_register(&isp->media_dev);
1062 }
1063
atomisp_initialize_modules(struct atomisp_device * isp)1064 static int atomisp_initialize_modules(struct atomisp_device *isp)
1065 {
1066 int ret;
1067
1068 ret = atomisp_mipi_csi2_init(isp);
1069 if (ret < 0) {
1070 dev_err(isp->dev, "mipi csi2 initialization failed\n");
1071 goto error_mipi_csi2;
1072 }
1073
1074 ret = atomisp_subdev_init(isp);
1075 if (ret < 0) {
1076 dev_err(isp->dev, "ISP subdev initialization failed\n");
1077 goto error_isp_subdev;
1078 }
1079
1080 return 0;
1081
1082 error_isp_subdev:
1083 error_mipi_csi2:
1084 atomisp_mipi_csi2_cleanup(isp);
1085 return ret;
1086 }
1087
atomisp_uninitialize_modules(struct atomisp_device * isp)1088 static void atomisp_uninitialize_modules(struct atomisp_device *isp)
1089 {
1090 atomisp_mipi_csi2_cleanup(isp);
1091 }
1092
1093 const struct firmware *
atomisp_load_firmware(struct atomisp_device * isp)1094 atomisp_load_firmware(struct atomisp_device *isp)
1095 {
1096 const struct firmware *fw;
1097 int rc;
1098 char *fw_path = NULL;
1099
1100 if ((isp->media_dev.hw_revision >> ATOMISP_HW_REVISION_SHIFT) ==
1101 ATOMISP_HW_REVISION_ISP2401)
1102 fw_path = "intel/ipu/shisp_2401a0_v21.bin";
1103
1104 if (isp->media_dev.hw_revision ==
1105 ((ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT) |
1106 ATOMISP_HW_STEPPING_A0))
1107 fw_path = "intel/ipu/shisp_2401a0_legacy_v21.bin";
1108
1109 if (isp->media_dev.hw_revision ==
1110 ((ATOMISP_HW_REVISION_ISP2400 << ATOMISP_HW_REVISION_SHIFT) |
1111 ATOMISP_HW_STEPPING_B0))
1112 fw_path = "intel/ipu/shisp_2400b0_v21.bin";
1113
1114 if (!fw_path) {
1115 dev_err(isp->dev, "Unsupported hw_revision 0x%x\n",
1116 isp->media_dev.hw_revision);
1117 return NULL;
1118 }
1119
1120 rc = request_firmware(&fw, fw_path, isp->dev);
1121 /* Fallback to old fw_path without "intel/ipu/" prefix */
1122 if (rc)
1123 rc = request_firmware(&fw, kbasename(fw_path), isp->dev);
1124 if (rc) {
1125 dev_err(isp->dev,
1126 "atomisp: Error %d while requesting firmware %s\n",
1127 rc, fw_path);
1128 return NULL;
1129 }
1130
1131 return fw;
1132 }
1133
atomisp_pm_init(struct atomisp_device * isp)1134 static void atomisp_pm_init(struct atomisp_device *isp)
1135 {
1136 /*
1137 * The atomisp does not use standard PCI power-management through the
1138 * PCI config space. Instead this driver directly tells the P-Unit to
1139 * disable the ISP over the IOSF. The standard PCI subsystem pm_ops will
1140 * try to access the config space before (resume) / after (suspend) this
1141 * driver has turned the ISP on / off, resulting in the following errors:
1142 *
1143 * "Unable to change power state from D0 to D3hot, device inaccessible"
1144 * "Unable to change power state from D3cold to D0, device inaccessible"
1145 *
1146 * To avoid these errors override the pm_domain so that all the PCI
1147 * subsys suspend / resume handling is skipped.
1148 */
1149 isp->pm_domain.ops.runtime_suspend = atomisp_power_off;
1150 isp->pm_domain.ops.runtime_resume = atomisp_power_on;
1151 isp->pm_domain.ops.suspend = atomisp_suspend;
1152 isp->pm_domain.ops.resume = atomisp_resume;
1153
1154 cpu_latency_qos_add_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
1155 dev_pm_domain_set(isp->dev, &isp->pm_domain);
1156
1157 pm_runtime_allow(isp->dev);
1158 pm_runtime_put_sync_suspend(isp->dev);
1159 }
1160
atomisp_pm_uninit(struct atomisp_device * isp)1161 static void atomisp_pm_uninit(struct atomisp_device *isp)
1162 {
1163 pm_runtime_get_sync(isp->dev);
1164 pm_runtime_forbid(isp->dev);
1165 dev_pm_domain_set(isp->dev, NULL);
1166 cpu_latency_qos_remove_request(&isp->pm_qos);
1167 }
1168
1169 #define ATOM_ISP_PCI_BAR 0
1170
atomisp_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)1171 static int atomisp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1172 {
1173 struct atomisp_device *isp;
1174 unsigned int start;
1175 u32 val;
1176 int err;
1177
1178 /* Pointer to struct device. */
1179 atomisp_dev = &pdev->dev;
1180
1181 start = pci_resource_start(pdev, ATOM_ISP_PCI_BAR);
1182 dev_dbg(&pdev->dev, "start: 0x%x\n", start);
1183
1184 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL);
1185 if (!isp)
1186 return -ENOMEM;
1187
1188 isp->dev = &pdev->dev;
1189 isp->saved_regs.ispmmadr = start;
1190 isp->asd.isp = isp;
1191
1192 mutex_init(&isp->mutex);
1193 spin_lock_init(&isp->lock);
1194
1195 /* This is not a true PCI device on SoC, so the delay is not needed. */
1196 pdev->d3hot_delay = 0;
1197
1198 pci_set_drvdata(pdev, isp);
1199
1200 switch (id->device) {
1201 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1202 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1203 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1204 isp->media_dev.hw_revision =
1205 (ATOMISP_HW_REVISION_ISP2400
1206 << ATOMISP_HW_REVISION_SHIFT) |
1207 ATOMISP_HW_STEPPING_B0;
1208
1209 switch (id->device) {
1210 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1211 isp->dfs = &dfs_config_merr_1179;
1212 break;
1213 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1214 isp->dfs = &dfs_config_merr_117a;
1215
1216 break;
1217 default:
1218 isp->dfs = &dfs_config_merr;
1219 break;
1220 }
1221 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1222 break;
1223 case ATOMISP_PCI_DEVICE_SOC_BYT:
1224 isp->media_dev.hw_revision =
1225 (ATOMISP_HW_REVISION_ISP2400
1226 << ATOMISP_HW_REVISION_SHIFT) |
1227 ATOMISP_HW_STEPPING_B0;
1228
1229 /*
1230 * Note: some Intel-based tablets with Android use a different
1231 * DFS table. Based on the comments at the Yocto Aero meta
1232 * version of this driver (at the ssid.h header), they're
1233 * identified via a "spid" var:
1234 *
1235 * androidboot.spid=vend:cust:manu:plat:prod:hard
1236 *
1237 * As we don't have this upstream, nor we know enough details
1238 * to use a DMI or PCI match table, the old code was just
1239 * removed, but let's keep a note here as a reminder that,
1240 * for certain devices, we may need to limit the max DFS
1241 * frequency to be below certain values, adjusting the
1242 * resolution accordingly.
1243 */
1244 isp->dfs = &dfs_config_byt;
1245
1246 /*
1247 * HPLL frequency is known to be device-specific, but we don't
1248 * have specs yet for exactly how it varies. Default to
1249 * BYT-CR but let provisioning set it via EFI variable
1250 */
1251 isp->hpll_freq = gmin_get_var_int(&pdev->dev, false, "HpllFreq", HPLL_FREQ_2000MHZ);
1252
1253 /*
1254 * for BYT/CHT we are put isp into D3cold to avoid pci registers access
1255 * in power off. Set d3cold_delay to 0 since default 100ms is not
1256 * necessary.
1257 */
1258 pdev->d3cold_delay = 0;
1259 break;
1260 case ATOMISP_PCI_DEVICE_SOC_ANN:
1261 isp->media_dev.hw_revision = (ATOMISP_HW_REVISION_ISP2401
1262 << ATOMISP_HW_REVISION_SHIFT);
1263 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1264 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1265 isp->dfs = &dfs_config_merr;
1266 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1267 break;
1268 case ATOMISP_PCI_DEVICE_SOC_CHT:
1269 isp->media_dev.hw_revision = (ATOMISP_HW_REVISION_ISP2401
1270 << ATOMISP_HW_REVISION_SHIFT);
1271 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1272 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1273
1274 isp->dfs = &dfs_config_cht;
1275 pdev->d3cold_delay = 0;
1276
1277 iosf_mbi_read(BT_MBI_UNIT_CCK, MBI_REG_READ, CCK_FUSE_REG_0, &val);
1278 switch (val & CCK_FUSE_HPLL_FREQ_MASK) {
1279 case 0x00:
1280 isp->hpll_freq = HPLL_FREQ_800MHZ;
1281 break;
1282 case 0x01:
1283 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1284 break;
1285 case 0x02:
1286 isp->hpll_freq = HPLL_FREQ_2000MHZ;
1287 break;
1288 default:
1289 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1290 dev_warn(&pdev->dev, "read HPLL from cck failed. Default to 1600 MHz.\n");
1291 }
1292 break;
1293 default:
1294 dev_err(&pdev->dev, "un-supported IUNIT device\n");
1295 return -ENODEV;
1296 }
1297
1298 if (pdev->revision <= ATOMISP_PCI_REV_BYT_A0_MAX) {
1299 dev_err(&pdev->dev, "revision %d is not supported\n", pdev->revision);
1300 return -ENODEV;
1301 }
1302
1303 dev_info(&pdev->dev, "ISP HPLL frequency base = %d MHz\n", isp->hpll_freq);
1304
1305 isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY;
1306
1307 /* Load isp firmware from user space */
1308 isp->firmware = atomisp_load_firmware(isp);
1309 if (!isp->firmware) {
1310 /* No firmware continue in pm-only mode for S0i3 support */
1311 dev_info(&pdev->dev, "Continuing in power-management only mode\n");
1312 isp->pm_only = true;
1313 atomisp_pm_init(isp);
1314 return 0;
1315 }
1316
1317 err = sh_css_check_firmware_version(isp->dev, isp->firmware->data);
1318 if (err) {
1319 dev_dbg(&pdev->dev, "Firmware version check failed\n");
1320 goto error_release_firmware;
1321 }
1322
1323 err = pcim_enable_device(pdev);
1324 if (err) {
1325 dev_err(&pdev->dev, "Failed to enable ISP PCI device (%d)\n", err);
1326 goto error_release_firmware;
1327 }
1328
1329 err = pcim_iomap_regions(pdev, BIT(ATOM_ISP_PCI_BAR), pci_name(pdev));
1330 if (err) {
1331 dev_err(&pdev->dev, "Failed to I/O memory remapping (%d)\n", err);
1332 goto error_release_firmware;
1333 }
1334
1335 isp->base = pcim_iomap_table(pdev)[ATOM_ISP_PCI_BAR];
1336
1337 pci_set_master(pdev);
1338
1339 err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1340 if (err < 0) {
1341 dev_err(&pdev->dev, "Failed to enable msi (%d)\n", err);
1342 goto error_release_firmware;
1343 }
1344
1345 atomisp_msi_irq_init(isp);
1346
1347 /*
1348 * for MRFLD, Software/firmware needs to write a 1 to bit 0 of
1349 * the register at CSI_RECEIVER_SELECTION_REG to enable SH CSI
1350 * backend write 0 will enable Arasan CSI backend, which has
1351 * bugs(like sighting:4567697 and 4567699) and will be removed
1352 * in B0
1353 */
1354 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
1355
1356 switch (id->device) {
1357 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1358 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1359 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1360 /*
1361 * Workaround for imbalance data eye issue which is observed
1362 * on TNG B0.
1363 */
1364 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, &val);
1365 val &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1366 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1367 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT));
1368 val |= (MRFLD_PCI_CSI1_HSRXCLKTRIM << MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1369 (MRFLD_PCI_CSI2_HSRXCLKTRIM << MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1370 (MRFLD_PCI_CSI3_HSRXCLKTRIM << MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT);
1371 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, val);
1372 break;
1373 default:
1374 break;
1375 }
1376
1377 err = atomisp_initialize_modules(isp);
1378 if (err < 0) {
1379 dev_err(&pdev->dev, "atomisp_initialize_modules (%d)\n", err);
1380 goto error_irq_uninit;
1381 }
1382
1383 err = atomisp_register_entities(isp);
1384 if (err < 0) {
1385 dev_err(&pdev->dev, "atomisp_register_entities failed (%d)\n", err);
1386 goto error_uninitialize_modules;
1387 }
1388
1389 INIT_WORK(&isp->assert_recovery_work, atomisp_assert_recovery_work);
1390
1391 /* save the iunit context only once after all the values are init'ed. */
1392 atomisp_save_iunit_reg(isp);
1393
1394 /* Init ISP memory management */
1395 hmm_init();
1396
1397 err = devm_request_threaded_irq(&pdev->dev, pdev->irq,
1398 atomisp_isr, atomisp_isr_thread,
1399 IRQF_SHARED, "isp_irq", isp);
1400 if (err) {
1401 dev_err(&pdev->dev, "Failed to request irq (%d)\n", err);
1402 goto error_unregister_entities;
1403 }
1404
1405 /* Load firmware into ISP memory */
1406 err = atomisp_css_load_firmware(isp);
1407 if (err) {
1408 dev_err(&pdev->dev, "Failed to init css.\n");
1409 goto error_free_irq;
1410 }
1411 /* Clear FW image from memory */
1412 release_firmware(isp->firmware);
1413 isp->firmware = NULL;
1414 isp->css_env.isp_css_fw.data = NULL;
1415
1416 atomisp_pm_init(isp);
1417
1418 err = v4l2_async_nf_register(&isp->notifier);
1419 if (err) {
1420 dev_err(isp->dev, "failed to register async notifier : %d\n", err);
1421 goto error_unload_firmware;
1422 }
1423
1424 return 0;
1425
1426 error_unload_firmware:
1427 atomisp_pm_uninit(isp);
1428 ia_css_unload_firmware();
1429 error_free_irq:
1430 devm_free_irq(&pdev->dev, pdev->irq, isp);
1431 error_unregister_entities:
1432 hmm_cleanup();
1433 atomisp_unregister_entities(isp);
1434 error_uninitialize_modules:
1435 atomisp_uninitialize_modules(isp);
1436 error_irq_uninit:
1437 atomisp_msi_irq_uninit(isp);
1438 pci_free_irq_vectors(pdev);
1439 error_release_firmware:
1440 release_firmware(isp->firmware);
1441 return err;
1442 }
1443
atomisp_pci_remove(struct pci_dev * pdev)1444 static void atomisp_pci_remove(struct pci_dev *pdev)
1445 {
1446 struct atomisp_device *isp = pci_get_drvdata(pdev);
1447
1448 atomisp_pm_uninit(isp);
1449
1450 if (isp->pm_only)
1451 return;
1452
1453 /* Undo ia_css_init() from atomisp_power_on() */
1454 atomisp_css_uninit(isp);
1455 ia_css_unload_firmware();
1456 devm_free_irq(&pdev->dev, pdev->irq, isp);
1457 hmm_cleanup();
1458
1459 atomisp_unregister_entities(isp);
1460 atomisp_uninitialize_modules(isp);
1461 atomisp_msi_irq_uninit(isp);
1462 pci_free_irq_vectors(pdev);
1463 }
1464
1465 static const struct pci_device_id atomisp_pci_tbl[] = {
1466 /* Merrifield */
1467 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD)},
1468 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_1179)},
1469 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_117A)},
1470 /* Baytrail */
1471 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_BYT)},
1472 /* Anniedale (Merrifield+ / Moorefield) */
1473 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_ANN)},
1474 /* Cherrytrail */
1475 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_CHT)},
1476 {0,}
1477 };
1478 MODULE_DEVICE_TABLE(pci, atomisp_pci_tbl);
1479
1480 static struct pci_driver atomisp_pci_driver = {
1481 .driver = {
1482 .dev_groups = dbg_attr_groups,
1483 },
1484 .name = "atomisp-isp2",
1485 .id_table = atomisp_pci_tbl,
1486 .probe = atomisp_pci_probe,
1487 .remove = atomisp_pci_remove,
1488 };
1489
1490 module_pci_driver(atomisp_pci_driver);
1491
1492 MODULE_AUTHOR("Wen Wang <wen.w.wang@intel.com>");
1493 MODULE_AUTHOR("Xiaolin Zhang <xiaolin.zhang@intel.com>");
1494 MODULE_LICENSE("GPL");
1495 MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver");
1496 MODULE_IMPORT_NS(INTEL_IPU_BRIDGE);
1497