1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. */ 3 /* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ 4 5 #ifndef WLAN_FIRMWARE_SERVICE_V01_H 6 #define WLAN_FIRMWARE_SERVICE_V01_H 7 8 #include <linux/soc/qcom/qmi.h> 9 10 #define WLFW_SERVICE_ID_V01 0x45 11 #define WLFW_SERVICE_VERS_V01 0x01 12 13 #define QMI_WLFW_SUBSYS_RESTART_LEVEL_RESP_V01 0x0055 14 #define QMI_WLFW_SUBSYS_RESTART_LEVEL_REQ_V01 0x0055 15 #define QMI_WLFW_POWER_SAVE_RESP_V01 0x0050 16 #define QMI_WLFW_CAP_REQ_V01 0x0024 17 #define QMI_WLFW_INI_FILE_DOWNLOAD_RESP_V01 0x0056 18 #define QMI_WLFW_CAL_REPORT_REQ_V01 0x0026 19 #define QMI_WLFW_M3_INFO_RESP_V01 0x003C 20 #define QMI_WLFW_CAL_REPORT_RESP_V01 0x0026 21 #define QMI_WLFW_PCIE_LINK_CTRL_RESP_V01 0x0059 22 #define QMI_WLFW_MAC_ADDR_RESP_V01 0x0033 23 #define QMI_WLFW_DYNAMIC_FEATURE_MASK_RESP_V01 0x003B 24 #define QMI_WLFW_IND_REGISTER_REQ_V01 0x0020 25 #define QMI_WLFW_DYNAMIC_FEATURE_MASK_REQ_V01 0x003B 26 #define QMI_WLFW_QDSS_TRACE_MODE_RESP_V01 0x0045 27 #define QMI_WLFW_AUX_UC_INFO_REQ_V01 0x005A 28 #define QMI_WLFW_FW_READY_IND_V01 0x0021 29 #define QMI_WLFW_SOFT_SKU_INFO_RESP_V01 0x0060 30 #define QMI_WLFW_QDSS_TRACE_MEM_INFO_RESP_V01 0x0040 31 #define QMI_WLFW_CAL_UPDATE_REQ_V01 0x0029 32 #define QMI_WLFW_PHY_CAP_REQ_V01 0x0057 33 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 34 #define QMI_WLFW_QDSS_TRACE_DATA_RESP_V01 0x0042 35 #define QMI_WLFW_RESPOND_MEM_RESP_V01 0x0036 36 #define QMI_WLFW_VBATT_RESP_V01 0x0032 37 #define QMI_WLFW_QDSS_TRACE_MODE_REQ_V01 0x0045 38 #define QMI_WLFW_CAL_DOWNLOAD_REQ_V01 0x0027 39 #define QMI_WLFW_IND_REGISTER_RESP_V01 0x0020 40 #define QMI_WLFW_CAL_UPDATE_RESP_V01 0x0029 41 #define QMI_WLFW_BMPS_CTRL_RESP_V01 0x005D 42 #define QMI_WLFW_LPASS_SSR_RESP_V01 0x005E 43 #define QMI_WLFW_AUX_UC_INFO_RESP_V01 0x005A 44 #define QMI_WLFW_M3_INFO_REQ_V01 0x003C 45 #define QMI_WLFW_PCIE_GEN_SWITCH_REQ_V01 0x0053 46 #define QMI_WLFW_ANTENNA_GRANT_RESP_V01 0x0048 47 #define QMI_WLFW_INITIATE_CAL_UPDATE_IND_V01 0x002A 48 #define QMI_WLFW_RESPOND_MEM_REQ_V01 0x0036 49 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 50 #define QMI_WLFW_MSA_READY_IND_V01 0x002B 51 #define QMI_WLFW_WLAN_MODE_REQ_V01 0x0022 52 #define QMI_WLFW_WLAN_CFG_RESP_V01 0x0023 53 #define QMI_WLFW_REJUVENATE_IND_V01 0x0039 54 #define QMI_WLFW_ATHDIAG_WRITE_REQ_V01 0x0031 55 #define QMI_WLFW_SOC_WAKE_REQ_V01 0x004F 56 #define QMI_WLFW_PIN_CONNECT_RESULT_IND_V01 0x002C 57 #define QMI_WLFW_M3_DUMP_UPLOAD_DONE_RESP_V01 0x004E 58 #define QMI_WLFW_QDSS_TRACE_SAVE_IND_V01 0x0041 59 #define QMI_WLFW_DRIVER_ASYNC_DATA_IND_V01 0x0061 60 #define QMI_WLFW_BDF_DOWNLOAD_RESP_V01 0x0025 61 #define QMI_WLFW_REJUVENATE_ACK_RESP_V01 0x003A 62 #define QMI_WLFW_MSA_INFO_RESP_V01 0x002D 63 #define QMI_WLFW_TME_LITE_INFO_RESP_V01 0x005B 64 #define QMI_WLFW_SHUTDOWN_REQ_V01 0x0043 65 #define QMI_WLFW_VBATT_REQ_V01 0x0032 66 #define QMI_WLFW_PCIE_LINK_CTRL_REQ_V01 0x0059 67 #define QMI_WLFW_MAC_ADDR_REQ_V01 0x0033 68 #define QMI_WLFW_WLAN_CFG_REQ_V01 0x0023 69 #define QMI_WLFW_MLO_RECONFIG_INFO_REQ_V01 0x005F 70 #define QMI_WLFW_ANTENNA_GRANT_REQ_V01 0x0048 71 #define QMI_WLFW_BDF_DOWNLOAD_REQ_V01 0x0025 72 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 73 #define QMI_WLFW_WLAN_HW_INIT_CFG_REQ_V01 0x0058 74 #define QMI_WLFW_RESPOND_GET_INFO_IND_V01 0x004B 75 #define QMI_WLFW_QDSS_TRACE_DATA_REQ_V01 0x0042 76 #define QMI_WLFW_LPASS_SSR_REQ_V01 0x005E 77 #define QMI_WLFW_MLO_RECONFIG_INFO_RESP_V01 0x005F 78 #define QMI_WLFW_CAL_DOWNLOAD_RESP_V01 0x0027 79 #define QMI_WLFW_INI_RESP_V01 0x002F 80 #define QMI_WLFW_QDSS_TRACE_MEM_INFO_REQ_V01 0x0040 81 #define QMI_WLFW_ANTENNA_SWITCH_REQ_V01 0x0047 82 #define QMI_WLFW_QDSS_TRACE_REQ_MEM_IND_V01 0x003F 83 #define QMI_WLFW_INITIATE_CAL_DOWNLOAD_IND_V01 0x0028 84 #define QMI_WLFW_ATHDIAG_WRITE_RESP_V01 0x0031 85 #define QMI_WLFW_FW_SSR_IND_V01 0x005C 86 #define QMI_WLFW_PHY_CAP_RESP_V01 0x0057 87 #define QMI_WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_RESP_V01 0x0044 88 #define QMI_WLFW_SOC_WAKE_RESP_V01 0x004F 89 #define QMI_WLFW_GET_INFO_RESP_V01 0x004A 90 #define QMI_WLFW_BMPS_CTRL_REQ_V01 0x005D 91 #define QMI_WLFW_PCIE_GEN_SWITCH_RESP_V01 0x0053 92 #define QMI_WLFW_INI_REQ_V01 0x002F 93 #define QMI_WLFW_M3_DUMP_UPLOAD_SEGMENTS_REQ_IND_V01 0x0054 94 #define QMI_WLFW_MSA_READY_REQ_V01 0x002E 95 #define QMI_WLFW_M3_DUMP_UPLOAD_DONE_REQ_V01 0x004E 96 #define QMI_WLFW_CAP_RESP_V01 0x0024 97 #define QMI_WLFW_REJUVENATE_ACK_REQ_V01 0x003A 98 #define QMI_WLFW_ATHDIAG_READ_RESP_V01 0x0030 99 #define QMI_WLFW_ANTENNA_SWITCH_RESP_V01 0x0047 100 #define QMI_WLFW_DEVICE_INFO_REQ_V01 0x004C 101 #define QMI_WLFW_MSA_INFO_REQ_V01 0x002D 102 #define QMI_WLFW_HOST_CAP_REQ_V01 0x0034 103 #define QMI_WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_V01 0x0044 104 #define QMI_WLFW_GET_INFO_REQ_V01 0x004A 105 #define QMI_WLFW_SOFT_SKU_INFO_REQ_V01 0x0060 106 #define QMI_WLFW_CAL_DONE_IND_V01 0x003E 107 #define QMI_WLFW_M3_DUMP_UPLOAD_REQ_IND_V01 0x004D 108 #define QMI_WLFW_WFC_CALL_STATUS_RESP_V01 0x0049 109 #define QMI_WLFW_FW_INIT_DONE_IND_V01 0x0038 110 #define QMI_WLFW_POWER_SAVE_REQ_V01 0x0050 111 #define QMI_WLFW_XO_CAL_IND_V01 0x003D 112 #define QMI_WLFW_SHUTDOWN_RESP_V01 0x0043 113 #define QMI_WLFW_ATHDIAG_READ_REQ_V01 0x0030 114 #define QMI_WLFW_WFC_CALL_TWT_CONFIG_IND_V01 0x0051 115 #define QMI_WLFW_WLAN_MODE_RESP_V01 0x0022 116 #define QMI_WLFW_WFC_CALL_STATUS_REQ_V01 0x0049 117 #define QMI_WLFW_DEVICE_INFO_RESP_V01 0x004C 118 #define QMI_WLFW_MSA_READY_RESP_V01 0x002E 119 #define QMI_WLFW_WLAN_HW_INIT_CFG_RESP_V01 0x0058 120 #define QMI_WLFW_INI_FILE_DOWNLOAD_REQ_V01 0x0056 121 #define QMI_WLFW_QDSS_TRACE_FREE_IND_V01 0x0046 122 #define QMI_WLFW_TME_LITE_INFO_REQ_V01 0x005B 123 #define QMI_WLFW_QDSS_MEM_READY_IND_V01 0x0052 124 125 #define QMI_WLFW_MAX_NUM_CAL_V01 5 126 #define QMI_WLFW_MAX_PLATFORM_NAME_LEN_V01 64 127 #define QMI_WLFW_MAX_HOST_DDR_RANGE_SIZE_V01 3 128 #define QMI_WLFW_MAX_MLO_CHIP_V01 3 129 #define QMI_WLFW_MAX_NUM_SHADOW_REG_V01 24 130 #define QMI_WLFW_MAX_BUILD_ID_LEN_V01 128 131 #define QMI_WLFW_MAX_DEV_MEM_NUM_V01 4 132 #define QMI_WLFW_MAX_NUM_SHARE_MEM_V01 8 133 #define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2 134 #define QMI_WLFW_MAX_NUM_SVC_V01 24 135 #define QMI_WLFW_MAX_NUM_MEMORY_REGIONS_V01 2 136 #define QMI_WLFW_MAC_ADDR_SIZE_V01 6 137 #define QMI_WLFW_MAX_NUM_GPIO_INFO_V01 20 138 #define QMI_WLFW_MLO_V2_CHP_V01 4 139 #define QMI_WLFW_MAX_NUM_MEM_CFG_V01 2 140 #define QMI_WLFW_PMU_PARAMS_MAX_V01 16 141 #define QMI_WLFW_MAX_NUM_MEM_SEG_V01 52 142 #define QMI_WLFW_MAX_WFC_CALL_STATUS_DATA_SIZE_V01 256 143 #define QMI_WLFW_MAX_DATA_SIZE_V01 6144 144 #define QMI_WLFW_FUNCTION_NAME_LEN_V01 128 145 #define QMI_WLFW_MAX_NUM_CE_V01 12 146 #define QMI_WLFW_MAX_TIMESTAMP_LEN_V01 32 147 #define QMI_WLFW_MAX_M3_SEGMENTS_SIZE_V01 10 148 #define QMI_WLFW_PMU_PIN_NAME_MAX_LEN_V01 32 149 #define QMI_WLFW_MAX_STR_LEN_V01 16 150 #define QMI_WLFW_MAX_NUM_SHADOW_REG_V3_V01 60 151 #define QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01 36 152 #define QMI_WLFW_MAX_ADJ_CHIP_V01 2 153 #define QMI_WLFW_MAX_NUM_SHADOW_REG_V3_USAGE_V01 40 154 #define QMI_WLFW_MAX_ATHDIAG_DATA_SIZE_V01 6144 155 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 156 157 enum wlfw_driver_mode_enum_v01 { 158 WLFW_DRIVER_MODE_ENUM_MIN_VAL_V01 = INT_MIN, 159 QMI_WLFW_MISSION_V01 = 0, 160 QMI_WLFW_FTM_V01 = 1, 161 QMI_WLFW_EPPING_V01 = 2, 162 QMI_WLFW_WALTEST_V01 = 3, 163 QMI_WLFW_OFF_V01 = 4, 164 QMI_WLFW_CCPM_V01 = 5, 165 QMI_WLFW_QVIT_V01 = 6, 166 QMI_WLFW_CALIBRATION_V01 = 7, 167 QMI_WLFW_FTM_CALIBRATION_V01 = 10, 168 WLFW_DRIVER_MODE_ENUM_MAX_VAL_V01 = INT_MAX, 169 }; 170 171 enum wlfw_cal_temp_id_enum_v01 { 172 WLFW_CAL_TEMP_ID_ENUM_MIN_VAL_V01 = INT_MIN, 173 QMI_WLFW_CAL_TEMP_IDX_0_V01 = 0, 174 QMI_WLFW_CAL_TEMP_IDX_1_V01 = 1, 175 QMI_WLFW_CAL_TEMP_IDX_2_V01 = 2, 176 QMI_WLFW_CAL_TEMP_IDX_3_V01 = 3, 177 QMI_WLFW_CAL_TEMP_IDX_4_V01 = 4, 178 WLFW_CAL_TEMP_ID_ENUM_MAX_VAL_V01 = INT_MAX, 179 }; 180 181 enum wlfw_pipedir_enum_v01 { 182 WLFW_PIPEDIR_ENUM_MIN_VAL_V01 = INT_MIN, 183 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 184 QMI_WLFW_PIPEDIR_IN_V01 = 1, 185 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 186 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 187 WLFW_PIPEDIR_ENUM_MAX_VAL_V01 = INT_MAX, 188 }; 189 190 enum wlfw_mem_type_enum_v01 { 191 WLFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 192 QMI_WLFW_MEM_TYPE_MSA_V01 = 0, 193 QMI_WLFW_MEM_TYPE_DDR_V01 = 1, 194 QMI_WLFW_MEM_BDF_V01 = 2, 195 QMI_WLFW_MEM_M3_V01 = 3, 196 QMI_WLFW_MEM_CAL_V01 = 4, 197 QMI_WLFW_MEM_DPD_V01 = 5, 198 QMI_WLFW_MEM_QDSS_V01 = 6, 199 QMI_WLFW_MEM_HANG_DATA_V01 = 7, 200 QMI_WLFW_MLO_GLOBAL_MEM_V01 = 8, 201 QMI_WLFW_PAGEABLE_MEM_V01 = 9, 202 QMI_WLFW_AFC_MEM_V01 = 10, 203 QMI_WLFW_MEM_LPASS_SHARED_V01 = 11, 204 QMI_WLFW_MEM_CALDB_SEG_V01 = 12, 205 WLFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 206 }; 207 208 enum wlfw_share_mem_type_enum_v01 { 209 WLFW_SHARE_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 210 QMI_WLFW_SHARE_MEM_CRASHDBG_V01 = 0, 211 QMI_WLFW_SHARE_MEM_TXSAR_V01 = 1, 212 QMI_WLFW_SHARE_MEM_AFC_V01 = 2, 213 QMI_WLFW_SHARE_MEM_REMOTE_COPY_V01 = 3, 214 QMI_WLFW_SHARE_MEM_MAX_V01 = 8, 215 WLFW_SHARE_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 216 }; 217 218 enum wlfw_qdss_trace_mode_enum_v01 { 219 WLFW_QDSS_TRACE_MODE_ENUM_MIN_VAL_V01 = INT_MIN, 220 QMI_WLFW_QDSS_TRACE_OFF_V01 = 0, 221 QMI_WLFW_QDSS_TRACE_ON_V01 = 1, 222 WLFW_QDSS_TRACE_MODE_ENUM_MAX_VAL_V01 = INT_MAX, 223 }; 224 225 enum wlfw_wfc_media_quality_v01 { 226 WLFW_WFC_MEDIA_QUALITY_MIN_VAL_V01 = INT_MIN, 227 QMI_WLFW_WFC_MEDIA_QUAL_NOT_AVAILABLE_V01 = 0, 228 QMI_WLFW_WFC_MEDIA_QUAL_BAD_V01 = 1, 229 QMI_WLFW_WFC_MEDIA_QUAL_GOOD_V01 = 2, 230 QMI_WLFW_WFC_MEDIA_QUAL_EXCELLENT_V01 = 3, 231 WLFW_WFC_MEDIA_QUALITY_MAX_VAL_V01 = INT_MAX, 232 }; 233 234 enum wlfw_soc_wake_enum_v01 { 235 WLFW_SOC_WAKE_ENUM_MIN_VAL_V01 = INT_MIN, 236 QMI_WLFW_WAKE_REQUEST_V01 = 0, 237 QMI_WLFW_WAKE_RELEASE_V01 = 1, 238 WLFW_SOC_WAKE_ENUM_MAX_VAL_V01 = INT_MAX, 239 }; 240 241 enum wlfw_host_build_type_v01 { 242 WLFW_HOST_BUILD_TYPE_MIN_VAL_V01 = INT_MIN, 243 QMI_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0, 244 QMI_HOST_BUILD_TYPE_PRIMARY_V01 = 1, 245 QMI_HOST_BUILD_TYPE_SECONDARY_V01 = 2, 246 WLFW_HOST_BUILD_TYPE_MAX_VAL_V01 = INT_MAX, 247 }; 248 249 enum wlfw_qmi_param_value_v01 { 250 WLFW_QMI_PARAM_VALUE_MIN_VAL_V01 = INT_MIN, 251 QMI_PARAM_INVALID_V01 = 0, 252 QMI_PARAM_ENABLE_V01 = 1, 253 QMI_PARAM_DISABLE_V01 = 2, 254 WLFW_QMI_PARAM_VALUE_MAX_VAL_V01 = INT_MAX, 255 }; 256 257 enum wlfw_rd_card_chain_cap_v01 { 258 WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN, 259 WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0, 260 WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1, 261 WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2, 262 WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX, 263 }; 264 265 enum wlfw_he_channel_width_cap_v01 { 266 WLFW_HE_CHANNEL_WIDTH_CAP_MIN_VAL_V01 = INT_MIN, 267 WLFW_PHY_HE_CHANNEL_WIDTH_CAP_UNSPECIFIED_V01 = 0, 268 WLFW_PHY_HE_CHANNEL_WIDTH_CAP_80MHZ_V01 = 1, 269 WLFW_PHY_HE_CHANNEL_WIDTH_CAP_160MHZ_V01 = 2, 270 WLFW_HE_CHANNEL_WIDTH_CAP_MAX_VAL_V01 = INT_MAX, 271 }; 272 273 enum wlfw_phy_qam_cap_v01 { 274 WLFW_PHY_QAM_CAP_MIN_VAL_V01 = INT_MIN, 275 WLFW_PHY_QAM_CAP_UNSPECIFIED_V01 = 0, 276 WLFW_PHY_QAM_CAP_1K_V01 = 1, 277 WLFW_PHY_QAM_CAP_4K_V01 = 2, 278 WLFW_PHY_QAM_CAP_MAX_VAL_V01 = INT_MAX, 279 }; 280 281 enum wlfw_pcie_gen_speed_v01 { 282 WLFW_PCIE_GEN_SPEED_MIN_VAL_V01 = INT_MIN, 283 QMI_PCIE_GEN_SPEED_INVALID_V01 = 0, 284 QMI_PCIE_GEN_SPEED_1_V01 = 1, 285 QMI_PCIE_GEN_SPEED_2_V01 = 2, 286 QMI_PCIE_GEN_SPEED_3_V01 = 3, 287 WLFW_PCIE_GEN_SPEED_MAX_VAL_V01 = INT_MAX, 288 }; 289 290 enum wlfw_power_save_mode_v01 { 291 WLFW_POWER_SAVE_MODE_MIN_VAL_V01 = INT_MIN, 292 WLFW_POWER_SAVE_ENTER_V01 = 0, 293 WLFW_POWER_SAVE_EXIT_V01 = 1, 294 WLFW_POWER_SAVE_MODE_MAX_VAL_V01 = INT_MAX, 295 }; 296 297 enum wlfw_m3_segment_type_v01 { 298 WLFW_M3_SEGMENT_TYPE_MIN_VAL_V01 = INT_MIN, 299 QMI_M3_SEGMENT_INVALID_V01 = 0, 300 QMI_M3_SEGMENT_PHYAREG_V01 = 1, 301 QMI_M3_SEGMENT_PHYDBG_V01 = 2, 302 QMI_M3_SEGMENT_WMAC0_REG_V01 = 3, 303 QMI_M3_SEGMENT_WCSSDBG_V01 = 4, 304 QMI_M3_SEGMENT_PHYAPDMEM_V01 = 5, 305 QMI_M3_SEGMENT_MAX_V01 = 6, 306 WLFW_M3_SEGMENT_TYPE_MAX_VAL_V01 = INT_MAX, 307 }; 308 309 enum cnss_feature_v01 { 310 CNSS_FEATURE_MIN_VAL_V01 = INT_MIN, 311 BOOTSTRAP_CLOCK_SELECT_V01 = 0, 312 CNSS_DRV_SUPPORT_V01 = 1, 313 CNSS_WLAN_EN_SUPPORT_V01 = 2, 314 CNSS_QDSS_CFG_MISS_V01 = 3, 315 CNSS_PCIE_PERST_NO_PULL_V01 = 4, 316 CNSS_RC_EP_ULTRASHORT_CHANNEL_V01 = 5, 317 CNSS_AUX_UC_SUPPORT_V01 = 6, 318 CNSS_MAX_FEATURE_V01 = 64, 319 CNSS_FEATURE_MAX_VAL_V01 = INT_MAX, 320 }; 321 322 enum wlfw_bdf_dnld_method_v01 { 323 WLFW_BDF_DNLD_METHOD_MIN_VAL_V01 = INT_MIN, 324 WLFW_DIRECT_BDF_COPY_V01 = 0, 325 WLFW_SEND_BDF_OVER_QMI_V01 = 1, 326 WLFW_BDF_DNLD_METHOD_MAX_VAL_V01 = INT_MAX, 327 }; 328 329 enum wlfw_gpio_info_type_v01 { 330 WLFW_GPIO_INFO_TYPE_MIN_VAL_V01 = INT_MIN, 331 WLAN_EN_GPIO_V01 = 0, 332 BT_EN_GPIO_V01 = 1, 333 HOST_SOL_GPIO_V01 = 2, 334 TARGET_SOL_GPIO_V01 = 3, 335 WLAN_SW_CTRL_GPIO_V01 = 4, 336 GPIO_TYPE_MAX_V01 = 5, 337 WLFW_GPIO_INFO_TYPE_MAX_VAL_V01 = INT_MAX, 338 }; 339 340 enum wlfw_ini_file_type_v01 { 341 WLFW_INI_FILE_TYPE_MIN_VAL_V01 = INT_MIN, 342 WLFW_INI_CFG_FILE_V01 = 0, 343 WLFW_CONN_ROAM_INI_V01 = 1, 344 WLFW_INI_FILE_TYPE_MAX_VAL_V01 = INT_MAX, 345 }; 346 347 enum wlfw_wlan_rf_subtype_v01 { 348 WLFW_WLAN_RF_SUBTYPE_MIN_VAL_V01 = INT_MIN, 349 WLFW_WLAN_RF_SLATE_V01 = 0, 350 WLFW_WLAN_RF_APACHE_V01 = 1, 351 WLFW_WLAN_RF_SUBTYPE_MAX_VAL_V01 = INT_MAX, 352 }; 353 354 enum wlfw_pcie_link_state_enum_v01 { 355 WLFW_PCIE_LINK_STATE_ENUM_MIN_VAL_V01 = INT_MIN, 356 QMI_WLFW_PCIE_ALLOW_LOW_PWR_V01 = 0, 357 QMI_WLFW_PCIE_PREVENT_LOW_PWR_V01 = 1, 358 WLFW_PCIE_LINK_STATE_ENUM_MAX_VAL_V01 = INT_MAX, 359 }; 360 361 enum wlfw_tme_lite_file_type_v01 { 362 WLFW_TME_LITE_FILE_TYPE_MIN_VAL_V01 = INT_MIN, 363 WLFW_TME_LITE_PATCH_FILE_V01 = 0, 364 WLFW_TME_LITE_OEM_FUSE_FILE_V01 = 1, 365 WLFW_TME_LITE_RPR_FILE_V01 = 2, 366 WLFW_TME_LITE_DPR_FILE_V01 = 3, 367 WLFW_TME_LITE_FILE_TYPE_MAX_VAL_V01 = INT_MAX, 368 }; 369 370 enum wlfw_bmps_state_enum_v01 { 371 WLFW_BMPS_STATE_ENUM_MIN_VAL_V01 = INT_MIN, 372 QMI_WLFW_BMPS_ENABLE_V01 = 0, 373 QMI_WLFW_BMPS_DISABLE_V01 = 1, 374 WLFW_BMPS_STATE_ENUM_MAX_VAL_V01 = INT_MAX, 375 }; 376 377 enum wlfw_fw_ssr_reason_v01 { 378 WLFW_FW_SSR_REASON_MIN_VAL_V01 = INT_MIN, 379 WLFW_FW_SSR_REASON_DEFAULT_V01 = 0, 380 WLFW_FW_SSR_REASON_XPAN_V01 = 1, 381 WLFW_FW_SSR_REASON_MAX_VAL_V01 = INT_MAX, 382 }; 383 384 enum wlfw_lpass_ssr_reason_v01 { 385 WLFW_LPASS_SSR_REASON_MIN_VAL_V01 = INT_MIN, 386 WLFW_LPASS_SSR_REASON_NON_CE_V01 = 0, 387 WLFW_LPASS_SSR_REASON_CE_V01 = 1, 388 WLFW_LPASS_SSR_REASON_MAX_VAL_V01 = INT_MAX, 389 }; 390 391 #define QMI_WLFW_CE_ATTR_FLAGS_V01 ((u32)0x00) 392 #define QMI_WLFW_CE_ATTR_NO_SNOOP_V01 ((u32)0x01) 393 #define QMI_WLFW_CE_ATTR_BYTE_SWAP_DATA_V01 ((u32)0x02) 394 #define QMI_WLFW_CE_ATTR_SWIZZLE_DESCRIPTORS_V01 ((u32)0x04) 395 #define QMI_WLFW_CE_ATTR_DISABLE_INTR_V01 ((u32)0x08) 396 #define QMI_WLFW_CE_ATTR_ENABLE_POLL_V01 ((u32)0x10) 397 398 #define QMI_WLFW_ALREADY_REGISTERED_V01 ((u64)0x01ULL) 399 #define QMI_WLFW_FW_READY_V01 ((u64)0x02ULL) 400 #define QMI_WLFW_MSA_READY_V01 ((u64)0x04ULL) 401 #define QMI_WLFW_FW_MEM_READY_V01 ((u64)0x08ULL) 402 #define QMI_WLFW_FW_INIT_DONE_V01 ((u64)0x10ULL) 403 404 #define QMI_WLFW_FW_REJUVENATE_V01 ((u64)0x01ULL) 405 406 #define QMI_WLFW_HW_XPA_V01 ((u64)0x01ULL) 407 #define QMI_WLFW_CBC_FILE_DOWNLOAD_V01 ((u64)0x02ULL) 408 409 #define QMI_WLFW_HOST_PCIE_GEN_SWITCH_V01 ((u64)0x01ULL) 410 #define QMI_WLFW_DIRECT_LINK_SUPPORT_V01 ((u64)0x02ULL) 411 #define QMI_WLFW_AUX_UC_SUPPORT_V01 ((u64)0x04ULL) 412 #define QMI_WLFW_CALDB_SEG_DDR_SUPPORT_V01 ((u64)0x08ULL) 413 414 #define QMI_WLFW_DIRECT_LINK_SKU_SUPPORT_V01 ((u64)0x01ULL) 415 416 struct wlfw_ce_tgt_pipe_cfg_s_v01 { 417 u32 pipe_num; 418 enum wlfw_pipedir_enum_v01 pipe_dir; 419 u32 nentries; 420 u32 nbytes_max; 421 u32 flags; 422 }; 423 424 struct wlfw_ce_svc_pipe_cfg_s_v01 { 425 u32 service_id; 426 enum wlfw_pipedir_enum_v01 pipe_dir; 427 u32 pipe_num; 428 }; 429 430 struct wlfw_shadow_reg_cfg_s_v01 { 431 u16 id; 432 u16 offset; 433 }; 434 435 struct wlfw_shadow_reg_v2_cfg_s_v01 { 436 u32 addr; 437 }; 438 439 struct wlfw_rri_over_ddr_cfg_s_v01 { 440 u32 base_addr_low; 441 u32 base_addr_high; 442 }; 443 444 struct wlfw_msi_cfg_s_v01 { 445 u16 ce_id; 446 u16 msi_vector; 447 }; 448 449 struct wlfw_memory_region_info_s_v01 { 450 u64 region_addr; 451 u32 size; 452 u8 secure_flag; 453 }; 454 455 struct wlfw_mem_cfg_s_v01 { 456 u64 offset; 457 u32 size; 458 u8 secure_flag; 459 }; 460 461 struct wlfw_mem_seg_s_v01 { 462 u32 size; 463 enum wlfw_mem_type_enum_v01 type; 464 u32 mem_cfg_len; 465 struct wlfw_mem_cfg_s_v01 mem_cfg[QMI_WLFW_MAX_NUM_MEM_CFG_V01]; 466 }; 467 468 struct wlfw_mem_seg_resp_s_v01 { 469 u64 addr; 470 u32 size; 471 enum wlfw_mem_type_enum_v01 type; 472 u8 restore; 473 }; 474 475 struct wlfw_rf_chip_info_s_v01 { 476 u32 chip_id; 477 u32 chip_family; 478 }; 479 480 struct wlfw_rf_board_info_s_v01 { 481 u32 board_id; 482 }; 483 484 struct wlfw_soc_info_s_v01 { 485 u32 soc_id; 486 }; 487 488 struct wlfw_fw_version_info_s_v01 { 489 u32 fw_version; 490 char fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN_V01 + 1]; 491 }; 492 493 struct wlfw_host_ddr_range_s_v01 { 494 u64 start; 495 u64 size; 496 }; 497 498 struct wlfw_m3_segment_info_s_v01 { 499 enum wlfw_m3_segment_type_v01 type; 500 u64 addr; 501 u64 size; 502 char name[QMI_WLFW_MAX_STR_LEN_V01 + 1]; 503 }; 504 505 struct wlfw_dev_mem_info_s_v01 { 506 u64 start; 507 u64 size; 508 }; 509 510 struct mlo_chip_info_s_v01 { 511 u8 chip_id; 512 u8 num_local_links; 513 u8 hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 514 u8 valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 515 }; 516 517 struct mlo_chip_v2_info_s_v01 { 518 struct mlo_chip_info_s_v01 mlo_chip_info; 519 u8 adj_mlo_num_chips; 520 struct mlo_chip_info_s_v01 adj_mlo_chip_info[QMI_WLFW_MAX_ADJ_CHIP_V01]; 521 }; 522 523 struct wlfw_pmu_param_v01 { 524 u8 pin_name[QMI_WLFW_PMU_PIN_NAME_MAX_LEN_V01]; 525 u32 wake_volt_valid; 526 u32 wake_volt; 527 u32 sleep_volt_valid; 528 u32 sleep_volt; 529 }; 530 531 struct wlfw_pmu_cfg_v01 { 532 u32 pmu_param_len; 533 struct wlfw_pmu_param_v01 pmu_param[QMI_WLFW_PMU_PARAMS_MAX_V01]; 534 }; 535 536 struct wlfw_shadow_reg_v3_cfg_s_v01 { 537 u32 addr; 538 }; 539 540 struct wlfw_share_mem_info_s_v01 { 541 enum wlfw_share_mem_type_enum_v01 type; 542 u64 start; 543 u64 size; 544 }; 545 546 struct wlfw_host_pcie_link_info_s_v01 { 547 u32 pci_link_speed; 548 u32 pci_link_width; 549 }; 550 551 struct wlchip_serial_id_v01 { 552 u32 serial_id_msb; 553 u32 serial_id_lsb; 554 }; 555 556 struct wlfw_ind_register_req_msg_v01 { 557 u8 fw_ready_enable_valid; 558 u8 fw_ready_enable; 559 u8 initiate_cal_download_enable_valid; 560 u8 initiate_cal_download_enable; 561 u8 initiate_cal_update_enable_valid; 562 u8 initiate_cal_update_enable; 563 u8 msa_ready_enable_valid; 564 u8 msa_ready_enable; 565 u8 pin_connect_result_enable_valid; 566 u8 pin_connect_result_enable; 567 u8 client_id_valid; 568 u32 client_id; 569 u8 request_mem_enable_valid; 570 u8 request_mem_enable; 571 u8 fw_mem_ready_enable_valid; 572 u8 fw_mem_ready_enable; 573 u8 fw_init_done_enable_valid; 574 u8 fw_init_done_enable; 575 u8 rejuvenate_enable_valid; 576 u32 rejuvenate_enable; 577 u8 xo_cal_enable_valid; 578 u8 xo_cal_enable; 579 u8 cal_done_enable_valid; 580 u8 cal_done_enable; 581 u8 qdss_trace_req_mem_enable_valid; 582 u8 qdss_trace_req_mem_enable; 583 u8 qdss_trace_save_enable_valid; 584 u8 qdss_trace_save_enable; 585 u8 qdss_trace_free_enable_valid; 586 u8 qdss_trace_free_enable; 587 u8 respond_get_info_enable_valid; 588 u8 respond_get_info_enable; 589 u8 m3_dump_upload_req_enable_valid; 590 u8 m3_dump_upload_req_enable; 591 u8 wfc_call_twt_config_enable_valid; 592 u8 wfc_call_twt_config_enable; 593 u8 qdss_mem_ready_enable_valid; 594 u8 qdss_mem_ready_enable; 595 u8 m3_dump_upload_segments_req_enable_valid; 596 u8 m3_dump_upload_segments_req_enable; 597 u8 fw_ssr_enable_valid; 598 u8 fw_ssr_enable; 599 u8 async_data_enable_valid; 600 u8 async_data_enable; 601 }; 602 #define WLFW_IND_REGISTER_REQ_MSG_V01_MAX_MSG_LEN 94 603 extern struct qmi_elem_info wlfw_ind_register_req_msg_v01_ei[]; 604 605 struct wlfw_ind_register_resp_msg_v01 { 606 struct qmi_response_type_v01 resp; 607 u8 fw_status_valid; 608 u64 fw_status; 609 }; 610 #define WLFW_IND_REGISTER_RESP_MSG_V01_MAX_MSG_LEN 18 611 extern struct qmi_elem_info wlfw_ind_register_resp_msg_v01_ei[]; 612 613 struct wlfw_fw_ready_ind_msg_v01 { 614 char placeholder; 615 }; 616 #define WLFW_FW_READY_IND_MSG_V01_MAX_MSG_LEN 0 617 extern struct qmi_elem_info wlfw_fw_ready_ind_msg_v01_ei[]; 618 619 struct wlfw_msa_ready_ind_msg_v01 { 620 u8 hang_data_addr_offset_valid; 621 u32 hang_data_addr_offset; 622 u8 hang_data_length_valid; 623 u16 hang_data_length; 624 }; 625 #define WLFW_MSA_READY_IND_MSG_V01_MAX_MSG_LEN 12 626 extern struct qmi_elem_info wlfw_msa_ready_ind_msg_v01_ei[]; 627 628 struct wlfw_pin_connect_result_ind_msg_v01 { 629 u8 pwr_pin_result_valid; 630 u32 pwr_pin_result; 631 u8 phy_io_pin_result_valid; 632 u32 phy_io_pin_result; 633 u8 rf_pin_result_valid; 634 u32 rf_pin_result; 635 }; 636 #define WLFW_PIN_CONNECT_RESULT_IND_MSG_V01_MAX_MSG_LEN 21 637 extern struct qmi_elem_info wlfw_pin_connect_result_ind_msg_v01_ei[]; 638 639 struct wlfw_wlan_mode_req_msg_v01 { 640 enum wlfw_driver_mode_enum_v01 mode; 641 u8 hw_debug_valid; 642 u8 hw_debug; 643 u8 xo_cal_data_valid; 644 u8 xo_cal_data; 645 u8 wlan_en_delay_valid; 646 u32 wlan_en_delay; 647 }; 648 #define WLFW_WLAN_MODE_REQ_MSG_V01_MAX_MSG_LEN 22 649 extern struct qmi_elem_info wlfw_wlan_mode_req_msg_v01_ei[]; 650 651 struct wlfw_wlan_mode_resp_msg_v01 { 652 struct qmi_response_type_v01 resp; 653 }; 654 #define WLFW_WLAN_MODE_RESP_MSG_V01_MAX_MSG_LEN 7 655 extern struct qmi_elem_info wlfw_wlan_mode_resp_msg_v01_ei[]; 656 657 struct wlfw_wlan_cfg_req_msg_v01 { 658 u8 host_version_valid; 659 char host_version[QMI_WLFW_MAX_STR_LEN_V01 + 1]; 660 u8 tgt_cfg_valid; 661 u32 tgt_cfg_len; 662 struct wlfw_ce_tgt_pipe_cfg_s_v01 tgt_cfg[QMI_WLFW_MAX_NUM_CE_V01]; 663 u8 svc_cfg_valid; 664 u32 svc_cfg_len; 665 struct wlfw_ce_svc_pipe_cfg_s_v01 svc_cfg[QMI_WLFW_MAX_NUM_SVC_V01]; 666 u8 shadow_reg_valid; 667 u32 shadow_reg_len; 668 struct wlfw_shadow_reg_cfg_s_v01 shadow_reg[QMI_WLFW_MAX_NUM_SHADOW_REG_V01]; 669 u8 shadow_reg_v2_valid; 670 u32 shadow_reg_v2_len; 671 struct wlfw_shadow_reg_v2_cfg_s_v01 shadow_reg_v2[QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01]; 672 u8 rri_over_ddr_cfg_valid; 673 struct wlfw_rri_over_ddr_cfg_s_v01 rri_over_ddr_cfg; 674 u8 msi_cfg_valid; 675 u32 msi_cfg_len; 676 struct wlfw_msi_cfg_s_v01 msi_cfg[QMI_WLFW_MAX_NUM_CE_V01]; 677 u8 shadow_reg_v3_valid; 678 u32 shadow_reg_v3_len; 679 struct wlfw_shadow_reg_v3_cfg_s_v01 shadow_reg_v3[QMI_WLFW_MAX_NUM_SHADOW_REG_V3_V01]; 680 }; 681 #define WLFW_WLAN_CFG_REQ_MSG_V01_MAX_MSG_LEN 1110 682 extern struct qmi_elem_info wlfw_wlan_cfg_req_msg_v01_ei[]; 683 684 struct wlfw_wlan_cfg_resp_msg_v01 { 685 struct qmi_response_type_v01 resp; 686 }; 687 #define WLFW_WLAN_CFG_RESP_MSG_V01_MAX_MSG_LEN 7 688 extern struct qmi_elem_info wlfw_wlan_cfg_resp_msg_v01_ei[]; 689 690 struct wlfw_cap_req_msg_v01 { 691 char placeholder; 692 }; 693 #define WLFW_CAP_REQ_MSG_V01_MAX_MSG_LEN 0 694 extern struct qmi_elem_info wlfw_cap_req_msg_v01_ei[]; 695 696 struct wlfw_cap_resp_msg_v01 { 697 struct qmi_response_type_v01 resp; 698 u8 chip_info_valid; 699 struct wlfw_rf_chip_info_s_v01 chip_info; 700 u8 board_info_valid; 701 struct wlfw_rf_board_info_s_v01 board_info; 702 u8 soc_info_valid; 703 struct wlfw_soc_info_s_v01 soc_info; 704 u8 fw_version_info_valid; 705 struct wlfw_fw_version_info_s_v01 fw_version_info; 706 u8 fw_build_id_valid; 707 char fw_build_id[QMI_WLFW_MAX_BUILD_ID_LEN_V01 + 1]; 708 u8 num_macs_valid; 709 u8 num_macs; 710 u8 voltage_mv_valid; 711 u32 voltage_mv; 712 u8 time_freq_hz_valid; 713 u32 time_freq_hz; 714 u8 otp_version_valid; 715 u32 otp_version; 716 u8 eeprom_caldata_read_timeout_valid; 717 u32 eeprom_caldata_read_timeout; 718 u8 fw_caps_valid; 719 u64 fw_caps; 720 u8 rd_card_chain_cap_valid; 721 enum wlfw_rd_card_chain_cap_v01 rd_card_chain_cap; 722 u8 dev_mem_info_valid; 723 struct wlfw_dev_mem_info_s_v01 dev_mem_info[QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 724 u8 foundry_name_valid; 725 char foundry_name[QMI_WLFW_MAX_STR_LEN_V01 + 1]; 726 u8 hang_data_addr_offset_valid; 727 u32 hang_data_addr_offset; 728 u8 hang_data_length_valid; 729 u16 hang_data_length; 730 u8 bdf_dnld_method_valid; 731 enum wlfw_bdf_dnld_method_v01 bdf_dnld_method; 732 u8 hwid_bitmap_valid; 733 u8 hwid_bitmap; 734 u8 ol_cpr_cfg_valid; 735 struct wlfw_pmu_cfg_v01 ol_cpr_cfg; 736 u8 regdb_mandatory_valid; 737 u8 regdb_mandatory; 738 u8 regdb_support_valid; 739 u8 regdb_support; 740 u8 rxgainlut_support_valid; 741 u8 rxgainlut_support; 742 u8 he_channel_width_cap_valid; 743 enum wlfw_he_channel_width_cap_v01 he_channel_width_cap; 744 u8 phy_qam_cap_valid; 745 enum wlfw_phy_qam_cap_v01 phy_qam_cap; 746 u8 serial_id_valid; 747 struct wlchip_serial_id_v01 serial_id; 748 }; 749 #define WLFW_CAP_RESP_MSG_V01_MAX_MSG_LEN 1171 750 extern struct qmi_elem_info wlfw_cap_resp_msg_v01_ei[]; 751 752 struct wlfw_bdf_download_req_msg_v01 { 753 u8 valid; 754 u8 file_id_valid; 755 enum wlfw_cal_temp_id_enum_v01 file_id; 756 u8 total_size_valid; 757 u32 total_size; 758 u8 seg_id_valid; 759 u32 seg_id; 760 u8 data_valid; 761 u32 data_len; 762 u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; 763 u8 end_valid; 764 u8 end; 765 u8 bdf_type_valid; 766 u8 bdf_type; 767 }; 768 #define WLFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN 6182 769 extern struct qmi_elem_info wlfw_bdf_download_req_msg_v01_ei[]; 770 771 struct wlfw_bdf_download_resp_msg_v01 { 772 struct qmi_response_type_v01 resp; 773 u8 host_bdf_data_valid; 774 u64 host_bdf_data; 775 }; 776 #define WLFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_MSG_LEN 18 777 extern struct qmi_elem_info wlfw_bdf_download_resp_msg_v01_ei[]; 778 779 struct wlfw_cal_report_req_msg_v01 { 780 u32 meta_data_len; 781 enum wlfw_cal_temp_id_enum_v01 meta_data[QMI_WLFW_MAX_NUM_CAL_V01]; 782 u8 xo_cal_data_valid; 783 u8 xo_cal_data; 784 u8 cal_remove_supported_valid; 785 u8 cal_remove_supported; 786 u8 cal_file_download_size_valid; 787 u64 cal_file_download_size; 788 }; 789 #define WLFW_CAL_REPORT_REQ_MSG_V01_MAX_MSG_LEN 43 790 extern struct qmi_elem_info wlfw_cal_report_req_msg_v01_ei[]; 791 792 struct wlfw_cal_report_resp_msg_v01 { 793 struct qmi_response_type_v01 resp; 794 }; 795 #define WLFW_CAL_REPORT_RESP_MSG_V01_MAX_MSG_LEN 7 796 extern struct qmi_elem_info wlfw_cal_report_resp_msg_v01_ei[]; 797 798 struct wlfw_initiate_cal_download_ind_msg_v01 { 799 enum wlfw_cal_temp_id_enum_v01 cal_id; 800 u8 total_size_valid; 801 u32 total_size; 802 u8 cal_data_location_valid; 803 u32 cal_data_location; 804 }; 805 #define WLFW_INITIATE_CAL_DOWNLOAD_IND_MSG_V01_MAX_MSG_LEN 21 806 extern struct qmi_elem_info wlfw_initiate_cal_download_ind_msg_v01_ei[]; 807 808 struct wlfw_cal_download_req_msg_v01 { 809 u8 valid; 810 u8 file_id_valid; 811 enum wlfw_cal_temp_id_enum_v01 file_id; 812 u8 total_size_valid; 813 u32 total_size; 814 u8 seg_id_valid; 815 u32 seg_id; 816 u8 data_valid; 817 u32 data_len; 818 u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; 819 u8 end_valid; 820 u8 end; 821 u8 cal_data_location_valid; 822 u32 cal_data_location; 823 }; 824 #define WLFW_CAL_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN 6185 825 extern struct qmi_elem_info wlfw_cal_download_req_msg_v01_ei[]; 826 827 struct wlfw_cal_download_resp_msg_v01 { 828 struct qmi_response_type_v01 resp; 829 }; 830 #define WLFW_CAL_DOWNLOAD_RESP_MSG_V01_MAX_MSG_LEN 7 831 extern struct qmi_elem_info wlfw_cal_download_resp_msg_v01_ei[]; 832 833 struct wlfw_initiate_cal_update_ind_msg_v01 { 834 enum wlfw_cal_temp_id_enum_v01 cal_id; 835 u32 total_size; 836 u8 cal_data_location_valid; 837 u32 cal_data_location; 838 }; 839 #define WLFW_INITIATE_CAL_UPDATE_IND_MSG_V01_MAX_MSG_LEN 21 840 extern struct qmi_elem_info wlfw_initiate_cal_update_ind_msg_v01_ei[]; 841 842 struct wlfw_cal_update_req_msg_v01 { 843 enum wlfw_cal_temp_id_enum_v01 cal_id; 844 u32 seg_id; 845 }; 846 #define WLFW_CAL_UPDATE_REQ_MSG_V01_MAX_MSG_LEN 14 847 extern struct qmi_elem_info wlfw_cal_update_req_msg_v01_ei[]; 848 849 struct wlfw_cal_update_resp_msg_v01 { 850 struct qmi_response_type_v01 resp; 851 u8 file_id_valid; 852 enum wlfw_cal_temp_id_enum_v01 file_id; 853 u8 total_size_valid; 854 u32 total_size; 855 u8 seg_id_valid; 856 u32 seg_id; 857 u8 data_valid; 858 u32 data_len; 859 u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; 860 u8 end_valid; 861 u8 end; 862 u8 cal_data_location_valid; 863 u32 cal_data_location; 864 }; 865 #define WLFW_CAL_UPDATE_RESP_MSG_V01_MAX_MSG_LEN 6188 866 extern struct qmi_elem_info wlfw_cal_update_resp_msg_v01_ei[]; 867 868 struct wlfw_msa_info_req_msg_v01 { 869 u64 msa_addr; 870 u32 size; 871 }; 872 #define WLFW_MSA_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 873 extern struct qmi_elem_info wlfw_msa_info_req_msg_v01_ei[]; 874 875 struct wlfw_msa_info_resp_msg_v01 { 876 struct qmi_response_type_v01 resp; 877 u32 mem_region_info_len; 878 struct wlfw_memory_region_info_s_v01 mem_region_info[QMI_WLFW_MAX_NUM_MEMORY_REGIONS_V01]; 879 }; 880 #define WLFW_MSA_INFO_RESP_MSG_V01_MAX_MSG_LEN 37 881 extern struct qmi_elem_info wlfw_msa_info_resp_msg_v01_ei[]; 882 883 struct wlfw_msa_ready_req_msg_v01 { 884 char placeholder; 885 }; 886 #define WLFW_MSA_READY_REQ_MSG_V01_MAX_MSG_LEN 0 887 extern struct qmi_elem_info wlfw_msa_ready_req_msg_v01_ei[]; 888 889 struct wlfw_msa_ready_resp_msg_v01 { 890 struct qmi_response_type_v01 resp; 891 }; 892 #define WLFW_MSA_READY_RESP_MSG_V01_MAX_MSG_LEN 7 893 extern struct qmi_elem_info wlfw_msa_ready_resp_msg_v01_ei[]; 894 895 struct wlfw_ini_req_msg_v01 { 896 u8 enablefwlog_valid; 897 u8 enablefwlog; 898 }; 899 #define WLFW_INI_REQ_MSG_V01_MAX_MSG_LEN 4 900 extern struct qmi_elem_info wlfw_ini_req_msg_v01_ei[]; 901 902 struct wlfw_ini_resp_msg_v01 { 903 struct qmi_response_type_v01 resp; 904 }; 905 #define WLFW_INI_RESP_MSG_V01_MAX_MSG_LEN 7 906 extern struct qmi_elem_info wlfw_ini_resp_msg_v01_ei[]; 907 908 struct wlfw_athdiag_read_req_msg_v01 { 909 u32 offset; 910 u32 mem_type; 911 u32 data_len; 912 }; 913 #define WLFW_ATHDIAG_READ_REQ_MSG_V01_MAX_MSG_LEN 21 914 extern struct qmi_elem_info wlfw_athdiag_read_req_msg_v01_ei[]; 915 916 struct wlfw_athdiag_read_resp_msg_v01 { 917 struct qmi_response_type_v01 resp; 918 u8 data_valid; 919 u32 data_len; 920 u8 data[QMI_WLFW_MAX_ATHDIAG_DATA_SIZE_V01]; 921 }; 922 #define WLFW_ATHDIAG_READ_RESP_MSG_V01_MAX_MSG_LEN 6156 923 extern struct qmi_elem_info wlfw_athdiag_read_resp_msg_v01_ei[]; 924 925 struct wlfw_athdiag_write_req_msg_v01 { 926 u32 offset; 927 u32 mem_type; 928 u32 data_len; 929 u8 data[QMI_WLFW_MAX_ATHDIAG_DATA_SIZE_V01]; 930 }; 931 #define WLFW_ATHDIAG_WRITE_REQ_MSG_V01_MAX_MSG_LEN 6163 932 extern struct qmi_elem_info wlfw_athdiag_write_req_msg_v01_ei[]; 933 934 struct wlfw_athdiag_write_resp_msg_v01 { 935 struct qmi_response_type_v01 resp; 936 }; 937 #define WLFW_ATHDIAG_WRITE_RESP_MSG_V01_MAX_MSG_LEN 7 938 extern struct qmi_elem_info wlfw_athdiag_write_resp_msg_v01_ei[]; 939 940 struct wlfw_vbatt_req_msg_v01 { 941 u64 voltage_uv; 942 }; 943 #define WLFW_VBATT_REQ_MSG_V01_MAX_MSG_LEN 11 944 extern struct qmi_elem_info wlfw_vbatt_req_msg_v01_ei[]; 945 946 struct wlfw_vbatt_resp_msg_v01 { 947 struct qmi_response_type_v01 resp; 948 }; 949 #define WLFW_VBATT_RESP_MSG_V01_MAX_MSG_LEN 7 950 extern struct qmi_elem_info wlfw_vbatt_resp_msg_v01_ei[]; 951 952 struct wlfw_mac_addr_req_msg_v01 { 953 u8 mac_addr_valid; 954 u8 mac_addr[QMI_WLFW_MAC_ADDR_SIZE_V01]; 955 }; 956 #define WLFW_MAC_ADDR_REQ_MSG_V01_MAX_MSG_LEN 9 957 extern struct qmi_elem_info wlfw_mac_addr_req_msg_v01_ei[]; 958 959 struct wlfw_mac_addr_resp_msg_v01 { 960 struct qmi_response_type_v01 resp; 961 }; 962 #define WLFW_MAC_ADDR_RESP_MSG_V01_MAX_MSG_LEN 7 963 extern struct qmi_elem_info wlfw_mac_addr_resp_msg_v01_ei[]; 964 965 struct wlfw_host_cap_req_msg_v01 { 966 u8 num_clients_valid; 967 u32 num_clients; 968 u8 wake_msi_valid; 969 u32 wake_msi; 970 u8 gpios_valid; 971 u32 gpios_len; 972 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 973 u8 nm_modem_valid; 974 u8 nm_modem; 975 u8 bdf_support_valid; 976 u8 bdf_support; 977 u8 bdf_cache_support_valid; 978 u8 bdf_cache_support; 979 u8 m3_support_valid; 980 u8 m3_support; 981 u8 m3_cache_support_valid; 982 u8 m3_cache_support; 983 u8 cal_filesys_support_valid; 984 u8 cal_filesys_support; 985 u8 cal_cache_support_valid; 986 u8 cal_cache_support; 987 u8 cal_done_valid; 988 u8 cal_done; 989 u8 mem_bucket_valid; 990 u32 mem_bucket; 991 u8 mem_cfg_mode_valid; 992 u8 mem_cfg_mode; 993 u8 cal_duration_valid; 994 u16 cal_duration; 995 u8 platform_name_valid; 996 char platform_name[QMI_WLFW_MAX_PLATFORM_NAME_LEN_V01 + 1]; 997 u8 ddr_range_valid; 998 struct wlfw_host_ddr_range_s_v01 ddr_range[QMI_WLFW_MAX_HOST_DDR_RANGE_SIZE_V01]; 999 u8 host_build_type_valid; 1000 enum wlfw_host_build_type_v01 host_build_type; 1001 u8 mlo_capable_valid; 1002 u8 mlo_capable; 1003 u8 mlo_chip_id_valid; 1004 u16 mlo_chip_id; 1005 u8 mlo_group_id_valid; 1006 u8 mlo_group_id; 1007 u8 max_mlo_peer_valid; 1008 u16 max_mlo_peer; 1009 u8 mlo_num_chips_valid; 1010 u8 mlo_num_chips; 1011 u8 mlo_chip_info_valid; 1012 struct mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_MLO_CHIP_V01]; 1013 u8 feature_list_valid; 1014 u64 feature_list; 1015 u8 num_wlan_clients_valid; 1016 u16 num_wlan_clients; 1017 u8 num_wlan_vaps_valid; 1018 u8 num_wlan_vaps; 1019 u8 wake_msi_addr_valid; 1020 u32 wake_msi_addr; 1021 u8 wlan_enable_delay_valid; 1022 u32 wlan_enable_delay; 1023 u8 ddr_type_valid; 1024 u32 ddr_type; 1025 u8 gpio_info_valid; 1026 u32 gpio_info_len; 1027 u32 gpio_info[QMI_WLFW_MAX_NUM_GPIO_INFO_V01]; 1028 u8 fw_ini_cfg_support_valid; 1029 u8 fw_ini_cfg_support; 1030 u8 mlo_chip_v2_info_valid; 1031 struct mlo_chip_v2_info_s_v01 mlo_chip_v2_info[QMI_WLFW_MLO_V2_CHP_V01]; 1032 u8 pcie_link_info_valid; 1033 struct wlfw_host_pcie_link_info_s_v01 pcie_link_info; 1034 }; 1035 #define WLFW_HOST_CAP_REQ_MSG_V01_MAX_MSG_LEN 581 1036 extern struct qmi_elem_info wlfw_host_cap_req_msg_v01_ei[]; 1037 1038 struct wlfw_host_cap_resp_msg_v01 { 1039 struct qmi_response_type_v01 resp; 1040 }; 1041 #define WLFW_HOST_CAP_RESP_MSG_V01_MAX_MSG_LEN 7 1042 extern struct qmi_elem_info wlfw_host_cap_resp_msg_v01_ei[]; 1043 1044 struct wlfw_request_mem_ind_msg_v01 { 1045 u32 mem_seg_len; 1046 struct wlfw_mem_seg_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; 1047 }; 1048 #define WLFW_REQUEST_MEM_IND_MSG_V01_MAX_MSG_LEN 1824 1049 extern struct qmi_elem_info wlfw_request_mem_ind_msg_v01_ei[]; 1050 1051 struct wlfw_respond_mem_req_msg_v01 { 1052 u32 mem_seg_len; 1053 struct wlfw_mem_seg_resp_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; 1054 }; 1055 #define WLFW_RESPOND_MEM_REQ_MSG_V01_MAX_MSG_LEN 888 1056 extern struct qmi_elem_info wlfw_respond_mem_req_msg_v01_ei[]; 1057 1058 struct wlfw_respond_mem_resp_msg_v01 { 1059 struct qmi_response_type_v01 resp; 1060 u8 share_mem_valid; 1061 u32 share_mem_len; 1062 struct wlfw_share_mem_info_s_v01 share_mem[QMI_WLFW_MAX_NUM_SHARE_MEM_V01]; 1063 }; 1064 #define WLFW_RESPOND_MEM_RESP_MSG_V01_MAX_MSG_LEN 171 1065 extern struct qmi_elem_info wlfw_respond_mem_resp_msg_v01_ei[]; 1066 1067 struct wlfw_fw_mem_ready_ind_msg_v01 { 1068 char placeholder; 1069 }; 1070 #define WLFW_FW_MEM_READY_IND_MSG_V01_MAX_MSG_LEN 0 1071 extern struct qmi_elem_info wlfw_fw_mem_ready_ind_msg_v01_ei[]; 1072 1073 struct wlfw_fw_init_done_ind_msg_v01 { 1074 u8 hang_data_addr_offset_valid; 1075 u32 hang_data_addr_offset; 1076 u8 hang_data_length_valid; 1077 u16 hang_data_length; 1078 u8 soft_sku_features_valid; 1079 u64 soft_sku_features; 1080 }; 1081 #define WLFW_FW_INIT_DONE_IND_MSG_V01_MAX_MSG_LEN 23 1082 extern struct qmi_elem_info wlfw_fw_init_done_ind_msg_v01_ei[]; 1083 1084 struct wlfw_rejuvenate_ind_msg_v01 { 1085 u8 cause_for_rejuvenation_valid; 1086 u8 cause_for_rejuvenation; 1087 u8 requesting_sub_system_valid; 1088 u8 requesting_sub_system; 1089 u8 line_number_valid; 1090 u16 line_number; 1091 u8 function_name_valid; 1092 char function_name[QMI_WLFW_FUNCTION_NAME_LEN_V01 + 1]; 1093 }; 1094 #define WLFW_REJUVENATE_IND_MSG_V01_MAX_MSG_LEN 144 1095 extern struct qmi_elem_info wlfw_rejuvenate_ind_msg_v01_ei[]; 1096 1097 struct wlfw_rejuvenate_ack_req_msg_v01 { 1098 char placeholder; 1099 }; 1100 #define WLFW_REJUVENATE_ACK_REQ_MSG_V01_MAX_MSG_LEN 0 1101 extern struct qmi_elem_info wlfw_rejuvenate_ack_req_msg_v01_ei[]; 1102 1103 struct wlfw_rejuvenate_ack_resp_msg_v01 { 1104 struct qmi_response_type_v01 resp; 1105 }; 1106 #define WLFW_REJUVENATE_ACK_RESP_MSG_V01_MAX_MSG_LEN 7 1107 extern struct qmi_elem_info wlfw_rejuvenate_ack_resp_msg_v01_ei[]; 1108 1109 struct wlfw_dynamic_feature_mask_req_msg_v01 { 1110 u8 mask_valid; 1111 u64 mask; 1112 }; 1113 #define WLFW_DYNAMIC_FEATURE_MASK_REQ_MSG_V01_MAX_MSG_LEN 11 1114 extern struct qmi_elem_info wlfw_dynamic_feature_mask_req_msg_v01_ei[]; 1115 1116 struct wlfw_dynamic_feature_mask_resp_msg_v01 { 1117 struct qmi_response_type_v01 resp; 1118 u8 prev_mask_valid; 1119 u64 prev_mask; 1120 u8 curr_mask_valid; 1121 u64 curr_mask; 1122 }; 1123 #define WLFW_DYNAMIC_FEATURE_MASK_RESP_MSG_V01_MAX_MSG_LEN 29 1124 extern struct qmi_elem_info wlfw_dynamic_feature_mask_resp_msg_v01_ei[]; 1125 1126 struct wlfw_m3_info_req_msg_v01 { 1127 u64 addr; 1128 u32 size; 1129 }; 1130 #define WLFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 1131 extern struct qmi_elem_info wlfw_m3_info_req_msg_v01_ei[]; 1132 1133 struct wlfw_m3_info_resp_msg_v01 { 1134 struct qmi_response_type_v01 resp; 1135 }; 1136 #define WLFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 1137 extern struct qmi_elem_info wlfw_m3_info_resp_msg_v01_ei[]; 1138 1139 struct wlfw_xo_cal_ind_msg_v01 { 1140 u8 xo_cal_data; 1141 }; 1142 #define WLFW_XO_CAL_IND_MSG_V01_MAX_MSG_LEN 4 1143 extern struct qmi_elem_info wlfw_xo_cal_ind_msg_v01_ei[]; 1144 1145 struct wlfw_cal_done_ind_msg_v01 { 1146 u8 cal_file_upload_size_valid; 1147 u64 cal_file_upload_size; 1148 }; 1149 #define WLFW_CAL_DONE_IND_MSG_V01_MAX_MSG_LEN 11 1150 extern struct qmi_elem_info wlfw_cal_done_ind_msg_v01_ei[]; 1151 1152 struct wlfw_qdss_trace_req_mem_ind_msg_v01 { 1153 u32 mem_seg_len; 1154 struct wlfw_mem_seg_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; 1155 }; 1156 #define WLFW_QDSS_TRACE_REQ_MEM_IND_MSG_V01_MAX_MSG_LEN 1824 1157 extern struct qmi_elem_info wlfw_qdss_trace_req_mem_ind_msg_v01_ei[]; 1158 1159 struct wlfw_qdss_trace_mem_info_req_msg_v01 { 1160 u32 mem_seg_len; 1161 struct wlfw_mem_seg_resp_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; 1162 u8 end_valid; 1163 u8 end; 1164 }; 1165 #define WLFW_QDSS_TRACE_MEM_INFO_REQ_MSG_V01_MAX_MSG_LEN 892 1166 extern struct qmi_elem_info wlfw_qdss_trace_mem_info_req_msg_v01_ei[]; 1167 1168 struct wlfw_qdss_trace_mem_info_resp_msg_v01 { 1169 struct qmi_response_type_v01 resp; 1170 }; 1171 #define WLFW_QDSS_TRACE_MEM_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 1172 extern struct qmi_elem_info wlfw_qdss_trace_mem_info_resp_msg_v01_ei[]; 1173 1174 struct wlfw_qdss_trace_save_ind_msg_v01 { 1175 u32 source; 1176 u32 total_size; 1177 u8 mem_seg_valid; 1178 u32 mem_seg_len; 1179 struct wlfw_mem_seg_resp_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; 1180 u8 file_name_valid; 1181 char file_name[QMI_WLFW_MAX_STR_LEN_V01 + 1]; 1182 }; 1183 #define WLFW_QDSS_TRACE_SAVE_IND_MSG_V01_MAX_MSG_LEN 921 1184 extern struct qmi_elem_info wlfw_qdss_trace_save_ind_msg_v01_ei[]; 1185 1186 struct wlfw_qdss_trace_data_req_msg_v01 { 1187 u32 seg_id; 1188 }; 1189 #define WLFW_QDSS_TRACE_DATA_REQ_MSG_V01_MAX_MSG_LEN 7 1190 extern struct qmi_elem_info wlfw_qdss_trace_data_req_msg_v01_ei[]; 1191 1192 struct wlfw_qdss_trace_data_resp_msg_v01 { 1193 struct qmi_response_type_v01 resp; 1194 u8 total_size_valid; 1195 u32 total_size; 1196 u8 seg_id_valid; 1197 u32 seg_id; 1198 u8 data_valid; 1199 u32 data_len; 1200 u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; 1201 u8 end_valid; 1202 u8 end; 1203 }; 1204 #define WLFW_QDSS_TRACE_DATA_RESP_MSG_V01_MAX_MSG_LEN 6174 1205 extern struct qmi_elem_info wlfw_qdss_trace_data_resp_msg_v01_ei[]; 1206 1207 struct wlfw_qdss_trace_config_download_req_msg_v01 { 1208 u8 total_size_valid; 1209 u32 total_size; 1210 u8 seg_id_valid; 1211 u32 seg_id; 1212 u8 data_valid; 1213 u32 data_len; 1214 u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; 1215 u8 end_valid; 1216 u8 end; 1217 }; 1218 #define WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN 6167 1219 extern struct qmi_elem_info wlfw_qdss_trace_config_download_req_msg_v01_ei[]; 1220 1221 struct wlfw_qdss_trace_config_download_resp_msg_v01 { 1222 struct qmi_response_type_v01 resp; 1223 }; 1224 #define WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_RESP_MSG_V01_MAX_MSG_LEN 7 1225 extern struct qmi_elem_info wlfw_qdss_trace_config_download_resp_msg_v01_ei[]; 1226 1227 struct wlfw_qdss_trace_mode_req_msg_v01 { 1228 u8 mode_valid; 1229 enum wlfw_qdss_trace_mode_enum_v01 mode; 1230 u8 option_valid; 1231 u64 option; 1232 u8 hw_trc_disable_override_valid; 1233 enum wlfw_qmi_param_value_v01 hw_trc_disable_override; 1234 }; 1235 #define WLFW_QDSS_TRACE_MODE_REQ_MSG_V01_MAX_MSG_LEN 25 1236 extern struct qmi_elem_info wlfw_qdss_trace_mode_req_msg_v01_ei[]; 1237 1238 struct wlfw_qdss_trace_mode_resp_msg_v01 { 1239 struct qmi_response_type_v01 resp; 1240 }; 1241 #define WLFW_QDSS_TRACE_MODE_RESP_MSG_V01_MAX_MSG_LEN 7 1242 extern struct qmi_elem_info wlfw_qdss_trace_mode_resp_msg_v01_ei[]; 1243 1244 struct wlfw_qdss_trace_free_ind_msg_v01 { 1245 u8 mem_seg_valid; 1246 u32 mem_seg_len; 1247 struct wlfw_mem_seg_resp_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; 1248 }; 1249 #define WLFW_QDSS_TRACE_FREE_IND_MSG_V01_MAX_MSG_LEN 888 1250 extern struct qmi_elem_info wlfw_qdss_trace_free_ind_msg_v01_ei[]; 1251 1252 struct wlfw_shutdown_req_msg_v01 { 1253 u8 shutdown_valid; 1254 u8 shutdown; 1255 }; 1256 #define WLFW_SHUTDOWN_REQ_MSG_V01_MAX_MSG_LEN 4 1257 extern struct qmi_elem_info wlfw_shutdown_req_msg_v01_ei[]; 1258 1259 struct wlfw_shutdown_resp_msg_v01 { 1260 struct qmi_response_type_v01 resp; 1261 }; 1262 #define WLFW_SHUTDOWN_RESP_MSG_V01_MAX_MSG_LEN 7 1263 extern struct qmi_elem_info wlfw_shutdown_resp_msg_v01_ei[]; 1264 1265 struct wlfw_antenna_switch_req_msg_v01 { 1266 char placeholder; 1267 }; 1268 #define WLFW_ANTENNA_SWITCH_REQ_MSG_V01_MAX_MSG_LEN 0 1269 extern struct qmi_elem_info wlfw_antenna_switch_req_msg_v01_ei[]; 1270 1271 struct wlfw_antenna_switch_resp_msg_v01 { 1272 struct qmi_response_type_v01 resp; 1273 u8 antenna_valid; 1274 u64 antenna; 1275 }; 1276 #define WLFW_ANTENNA_SWITCH_RESP_MSG_V01_MAX_MSG_LEN 18 1277 extern struct qmi_elem_info wlfw_antenna_switch_resp_msg_v01_ei[]; 1278 1279 struct wlfw_antenna_grant_req_msg_v01 { 1280 u8 grant_valid; 1281 u64 grant; 1282 }; 1283 #define WLFW_ANTENNA_GRANT_REQ_MSG_V01_MAX_MSG_LEN 11 1284 extern struct qmi_elem_info wlfw_antenna_grant_req_msg_v01_ei[]; 1285 1286 struct wlfw_antenna_grant_resp_msg_v01 { 1287 struct qmi_response_type_v01 resp; 1288 }; 1289 #define WLFW_ANTENNA_GRANT_RESP_MSG_V01_MAX_MSG_LEN 7 1290 extern struct qmi_elem_info wlfw_antenna_grant_resp_msg_v01_ei[]; 1291 1292 struct wlfw_wfc_call_status_req_msg_v01 { 1293 u32 wfc_call_status_len; 1294 u8 wfc_call_status[QMI_WLFW_MAX_WFC_CALL_STATUS_DATA_SIZE_V01]; 1295 u8 wfc_call_active_valid; 1296 u8 wfc_call_active; 1297 u8 all_wfc_calls_held_valid; 1298 u8 all_wfc_calls_held; 1299 u8 is_wfc_emergency_valid; 1300 u8 is_wfc_emergency; 1301 u8 twt_ims_start_valid; 1302 u64 twt_ims_start; 1303 u8 twt_ims_int_valid; 1304 u16 twt_ims_int; 1305 u8 media_quality_valid; 1306 enum wlfw_wfc_media_quality_v01 media_quality; 1307 }; 1308 #define WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN 296 1309 extern struct qmi_elem_info wlfw_wfc_call_status_req_msg_v01_ei[]; 1310 1311 struct wlfw_wfc_call_status_resp_msg_v01 { 1312 struct qmi_response_type_v01 resp; 1313 }; 1314 #define WLFW_WFC_CALL_STATUS_RESP_MSG_V01_MAX_MSG_LEN 7 1315 extern struct qmi_elem_info wlfw_wfc_call_status_resp_msg_v01_ei[]; 1316 1317 struct wlfw_get_info_req_msg_v01 { 1318 u8 type; 1319 u32 data_len; 1320 u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; 1321 }; 1322 #define WLFW_GET_INFO_REQ_MSG_V01_MAX_MSG_LEN 6153 1323 extern struct qmi_elem_info wlfw_get_info_req_msg_v01_ei[]; 1324 1325 struct wlfw_get_info_resp_msg_v01 { 1326 struct qmi_response_type_v01 resp; 1327 }; 1328 #define WLFW_GET_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 1329 extern struct qmi_elem_info wlfw_get_info_resp_msg_v01_ei[]; 1330 1331 struct wlfw_respond_get_info_ind_msg_v01 { 1332 u32 data_len; 1333 u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; 1334 u8 type_valid; 1335 u8 type; 1336 u8 is_last_valid; 1337 u8 is_last; 1338 u8 seq_no_valid; 1339 u32 seq_no; 1340 }; 1341 #define WLFW_RESPOND_GET_INFO_IND_MSG_V01_MAX_MSG_LEN 6164 1342 extern struct qmi_elem_info wlfw_respond_get_info_ind_msg_v01_ei[]; 1343 1344 struct wlfw_device_info_req_msg_v01 { 1345 char placeholder; 1346 }; 1347 #define WLFW_DEVICE_INFO_REQ_MSG_V01_MAX_MSG_LEN 0 1348 extern struct qmi_elem_info wlfw_device_info_req_msg_v01_ei[]; 1349 1350 struct wlfw_device_info_resp_msg_v01 { 1351 struct qmi_response_type_v01 resp; 1352 u8 bar_addr_valid; 1353 u64 bar_addr; 1354 u8 bar_size_valid; 1355 u32 bar_size; 1356 u8 mhi_state_info_addr_valid; 1357 u64 mhi_state_info_addr; 1358 u8 mhi_state_info_size_valid; 1359 u32 mhi_state_info_size; 1360 }; 1361 #define WLFW_DEVICE_INFO_RESP_MSG_V01_MAX_MSG_LEN 43 1362 extern struct qmi_elem_info wlfw_device_info_resp_msg_v01_ei[]; 1363 1364 struct wlfw_m3_dump_upload_req_ind_msg_v01 { 1365 u32 pdev_id; 1366 u64 addr; 1367 u64 size; 1368 }; 1369 #define WLFW_M3_DUMP_UPLOAD_REQ_IND_MSG_V01_MAX_MSG_LEN 29 1370 extern struct qmi_elem_info wlfw_m3_dump_upload_req_ind_msg_v01_ei[]; 1371 1372 struct wlfw_m3_dump_upload_done_req_msg_v01 { 1373 u32 pdev_id; 1374 u32 status; 1375 }; 1376 #define WLFW_M3_DUMP_UPLOAD_DONE_REQ_MSG_V01_MAX_MSG_LEN 14 1377 extern struct qmi_elem_info wlfw_m3_dump_upload_done_req_msg_v01_ei[]; 1378 1379 struct wlfw_m3_dump_upload_done_resp_msg_v01 { 1380 struct qmi_response_type_v01 resp; 1381 }; 1382 #define WLFW_M3_DUMP_UPLOAD_DONE_RESP_MSG_V01_MAX_MSG_LEN 7 1383 extern struct qmi_elem_info wlfw_m3_dump_upload_done_resp_msg_v01_ei[]; 1384 1385 struct wlfw_soc_wake_req_msg_v01 { 1386 u8 wake_valid; 1387 enum wlfw_soc_wake_enum_v01 wake; 1388 }; 1389 #define WLFW_SOC_WAKE_REQ_MSG_V01_MAX_MSG_LEN 7 1390 extern struct qmi_elem_info wlfw_soc_wake_req_msg_v01_ei[]; 1391 1392 struct wlfw_soc_wake_resp_msg_v01 { 1393 struct qmi_response_type_v01 resp; 1394 }; 1395 #define WLFW_SOC_WAKE_RESP_MSG_V01_MAX_MSG_LEN 7 1396 extern struct qmi_elem_info wlfw_soc_wake_resp_msg_v01_ei[]; 1397 1398 struct wlfw_power_save_req_msg_v01 { 1399 u8 power_save_mode_valid; 1400 enum wlfw_power_save_mode_v01 power_save_mode; 1401 }; 1402 #define WLFW_POWER_SAVE_REQ_MSG_V01_MAX_MSG_LEN 7 1403 extern struct qmi_elem_info wlfw_power_save_req_msg_v01_ei[]; 1404 1405 struct wlfw_power_save_resp_msg_v01 { 1406 struct qmi_response_type_v01 resp; 1407 }; 1408 #define WLFW_POWER_SAVE_RESP_MSG_V01_MAX_MSG_LEN 7 1409 extern struct qmi_elem_info wlfw_power_save_resp_msg_v01_ei[]; 1410 1411 struct wlfw_wfc_call_twt_config_ind_msg_v01 { 1412 u8 twt_sta_start_valid; 1413 u64 twt_sta_start; 1414 u8 twt_sta_int_valid; 1415 u16 twt_sta_int; 1416 u8 twt_sta_upo_valid; 1417 u16 twt_sta_upo; 1418 u8 twt_sta_sp_valid; 1419 u16 twt_sta_sp; 1420 u8 twt_sta_dl_valid; 1421 u16 twt_sta_dl; 1422 u8 twt_sta_config_changed_valid; 1423 u8 twt_sta_config_changed; 1424 }; 1425 #define WLFW_WFC_CALL_TWT_CONFIG_IND_MSG_V01_MAX_MSG_LEN 35 1426 extern struct qmi_elem_info wlfw_wfc_call_twt_config_ind_msg_v01_ei[]; 1427 1428 struct wlfw_qdss_mem_ready_ind_msg_v01 { 1429 char placeholder; 1430 }; 1431 #define WLFW_QDSS_MEM_READY_IND_MSG_V01_MAX_MSG_LEN 0 1432 extern struct qmi_elem_info wlfw_qdss_mem_ready_ind_msg_v01_ei[]; 1433 1434 struct wlfw_pcie_gen_switch_req_msg_v01 { 1435 enum wlfw_pcie_gen_speed_v01 pcie_speed; 1436 }; 1437 #define WLFW_PCIE_GEN_SWITCH_REQ_MSG_V01_MAX_MSG_LEN 7 1438 extern struct qmi_elem_info wlfw_pcie_gen_switch_req_msg_v01_ei[]; 1439 1440 struct wlfw_pcie_gen_switch_resp_msg_v01 { 1441 struct qmi_response_type_v01 resp; 1442 }; 1443 #define WLFW_PCIE_GEN_SWITCH_RESP_MSG_V01_MAX_MSG_LEN 7 1444 extern struct qmi_elem_info wlfw_pcie_gen_switch_resp_msg_v01_ei[]; 1445 1446 struct wlfw_m3_dump_upload_segments_req_ind_msg_v01 { 1447 u32 pdev_id; 1448 u32 no_of_valid_segments; 1449 struct wlfw_m3_segment_info_s_v01 m3_segment[QMI_WLFW_MAX_M3_SEGMENTS_SIZE_V01]; 1450 }; 1451 #define WLFW_M3_DUMP_UPLOAD_SEGMENTS_REQ_IND_MSG_V01_MAX_MSG_LEN 387 1452 extern struct qmi_elem_info wlfw_m3_dump_upload_segments_req_ind_msg_v01_ei[]; 1453 1454 struct wlfw_subsys_restart_level_req_msg_v01 { 1455 u8 restart_level_type_valid; 1456 u8 restart_level_type; 1457 }; 1458 #define WLFW_SUBSYS_RESTART_LEVEL_REQ_MSG_V01_MAX_MSG_LEN 4 1459 extern struct qmi_elem_info wlfw_subsys_restart_level_req_msg_v01_ei[]; 1460 1461 struct wlfw_subsys_restart_level_resp_msg_v01 { 1462 struct qmi_response_type_v01 resp; 1463 }; 1464 #define WLFW_SUBSYS_RESTART_LEVEL_RESP_MSG_V01_MAX_MSG_LEN 7 1465 extern struct qmi_elem_info wlfw_subsys_restart_level_resp_msg_v01_ei[]; 1466 1467 struct wlfw_ini_file_download_req_msg_v01 { 1468 u8 file_type_valid; 1469 enum wlfw_ini_file_type_v01 file_type; 1470 u8 total_size_valid; 1471 u32 total_size; 1472 u8 seg_id_valid; 1473 u32 seg_id; 1474 u8 data_valid; 1475 u32 data_len; 1476 u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; 1477 u8 end_valid; 1478 u8 end; 1479 }; 1480 #define WLFW_INI_FILE_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN 6174 1481 extern struct qmi_elem_info wlfw_ini_file_download_req_msg_v01_ei[]; 1482 1483 struct wlfw_ini_file_download_resp_msg_v01 { 1484 struct qmi_response_type_v01 resp; 1485 }; 1486 #define WLFW_INI_FILE_DOWNLOAD_RESP_MSG_V01_MAX_MSG_LEN 7 1487 extern struct qmi_elem_info wlfw_ini_file_download_resp_msg_v01_ei[]; 1488 1489 struct wlfw_phy_cap_req_msg_v01 { 1490 char placeholder; 1491 }; 1492 #define WLFW_PHY_CAP_REQ_MSG_V01_MAX_MSG_LEN 0 1493 extern struct qmi_elem_info wlfw_phy_cap_req_msg_v01_ei[]; 1494 1495 struct wlfw_phy_cap_resp_msg_v01 { 1496 struct qmi_response_type_v01 resp; 1497 u8 num_phy_valid; 1498 u8 num_phy; 1499 u8 board_id_valid; 1500 u32 board_id; 1501 u8 mlo_cap_v2_support_valid; 1502 u32 mlo_cap_v2_support; 1503 u8 single_chip_mlo_support_valid; 1504 u8 single_chip_mlo_support; 1505 }; 1506 #define WLFW_PHY_CAP_RESP_MSG_V01_MAX_MSG_LEN 29 1507 extern struct qmi_elem_info wlfw_phy_cap_resp_msg_v01_ei[]; 1508 1509 struct wlfw_wlan_hw_init_cfg_req_msg_v01 { 1510 u8 rf_subtype_valid; 1511 enum wlfw_wlan_rf_subtype_v01 rf_subtype; 1512 }; 1513 #define WLFW_WLAN_HW_INIT_CFG_REQ_MSG_V01_MAX_MSG_LEN 7 1514 extern struct qmi_elem_info wlfw_wlan_hw_init_cfg_req_msg_v01_ei[]; 1515 1516 struct wlfw_wlan_hw_init_cfg_resp_msg_v01 { 1517 struct qmi_response_type_v01 resp; 1518 }; 1519 #define WLFW_WLAN_HW_INIT_CFG_RESP_MSG_V01_MAX_MSG_LEN 7 1520 extern struct qmi_elem_info wlfw_wlan_hw_init_cfg_resp_msg_v01_ei[]; 1521 1522 struct wlfw_pcie_link_ctrl_req_msg_v01 { 1523 enum wlfw_pcie_link_state_enum_v01 link_state_req; 1524 }; 1525 #define WLFW_PCIE_LINK_CTRL_REQ_MSG_V01_MAX_MSG_LEN 7 1526 extern struct qmi_elem_info wlfw_pcie_link_ctrl_req_msg_v01_ei[]; 1527 1528 struct wlfw_pcie_link_ctrl_resp_msg_v01 { 1529 struct qmi_response_type_v01 resp; 1530 }; 1531 #define WLFW_PCIE_LINK_CTRL_RESP_MSG_V01_MAX_MSG_LEN 7 1532 extern struct qmi_elem_info wlfw_pcie_link_ctrl_resp_msg_v01_ei[]; 1533 1534 struct wlfw_aux_uc_info_req_msg_v01 { 1535 u64 addr; 1536 u32 size; 1537 }; 1538 #define WLFW_AUX_UC_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 1539 extern struct qmi_elem_info wlfw_aux_uc_info_req_msg_v01_ei[]; 1540 1541 struct wlfw_aux_uc_info_resp_msg_v01 { 1542 struct qmi_response_type_v01 resp; 1543 }; 1544 #define WLFW_AUX_UC_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 1545 extern struct qmi_elem_info wlfw_aux_uc_info_resp_msg_v01_ei[]; 1546 1547 struct wlfw_tme_lite_info_req_msg_v01 { 1548 enum wlfw_tme_lite_file_type_v01 tme_file; 1549 u64 addr; 1550 u32 size; 1551 }; 1552 #define WLFW_TME_LITE_INFO_REQ_MSG_V01_MAX_MSG_LEN 25 1553 extern struct qmi_elem_info wlfw_tme_lite_info_req_msg_v01_ei[]; 1554 1555 struct wlfw_tme_lite_info_resp_msg_v01 { 1556 struct qmi_response_type_v01 resp; 1557 }; 1558 #define WLFW_TME_LITE_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 1559 extern struct qmi_elem_info wlfw_tme_lite_info_resp_msg_v01_ei[]; 1560 1561 struct wlfw_soft_sku_info_req_msg_v01 { 1562 u64 addr; 1563 u32 size; 1564 }; 1565 #define WLFW_SOFT_SKU_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 1566 extern struct qmi_elem_info wlfw_soft_sku_info_req_msg_v01_ei[]; 1567 1568 struct wlfw_soft_sku_info_resp_msg_v01 { 1569 struct qmi_response_type_v01 resp; 1570 }; 1571 #define WLFW_SOFT_SKU_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 1572 extern struct qmi_elem_info wlfw_soft_sku_info_resp_msg_v01_ei[]; 1573 1574 struct wlfw_fw_ssr_ind_msg_v01 { 1575 enum wlfw_fw_ssr_reason_v01 reason_code; 1576 }; 1577 #define WLFW_FW_SSR_IND_MSG_V01_MAX_MSG_LEN 7 1578 extern struct qmi_elem_info wlfw_fw_ssr_ind_msg_v01_ei[]; 1579 1580 struct wlfw_bmps_ctrl_req_msg_v01 { 1581 enum wlfw_bmps_state_enum_v01 bmps_state; 1582 }; 1583 #define WLFW_BMPS_CTRL_REQ_MSG_V01_MAX_MSG_LEN 7 1584 extern struct qmi_elem_info wlfw_bmps_ctrl_req_msg_v01_ei[]; 1585 1586 struct wlfw_bmps_ctrl_resp_msg_v01 { 1587 struct qmi_response_type_v01 resp; 1588 }; 1589 #define WLFW_BMPS_CTRL_RESP_MSG_V01_MAX_MSG_LEN 7 1590 extern struct qmi_elem_info wlfw_bmps_ctrl_resp_msg_v01_ei[]; 1591 1592 struct wlfw_lpass_ssr_req_msg_v01 { 1593 enum wlfw_lpass_ssr_reason_v01 reason_code; 1594 }; 1595 #define WLFW_LPASS_SSR_REQ_MSG_V01_MAX_MSG_LEN 7 1596 extern struct qmi_elem_info wlfw_lpass_ssr_req_msg_v01_ei[]; 1597 1598 struct wlfw_lpass_ssr_resp_msg_v01 { 1599 struct qmi_response_type_v01 resp; 1600 }; 1601 #define WLFW_LPASS_SSR_RESP_MSG_V01_MAX_MSG_LEN 7 1602 extern struct qmi_elem_info wlfw_lpass_ssr_resp_msg_v01_ei[]; 1603 1604 struct wlfw_mlo_reconfig_info_req_msg_v01 { 1605 u8 mlo_capable_valid; 1606 u8 mlo_capable; 1607 u8 mlo_chip_id_valid; 1608 u16 mlo_chip_id; 1609 u8 mlo_group_id_valid; 1610 u8 mlo_group_id; 1611 u8 max_mlo_peer_valid; 1612 u16 max_mlo_peer; 1613 u8 mlo_num_chips_valid; 1614 u8 mlo_num_chips; 1615 u8 mlo_chip_info_valid; 1616 struct mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_MLO_CHIP_V01]; 1617 u8 mlo_chip_v2_info_valid; 1618 struct mlo_chip_v2_info_s_v01 mlo_chip_v2_info[QMI_WLFW_MLO_V2_CHP_V01]; 1619 }; 1620 #define WLFW_MLO_RECONFIG_INFO_REQ_MSG_V01_MAX_MSG_LEN 122 1621 extern struct qmi_elem_info wlfw_mlo_reconfig_info_req_msg_v01_ei[]; 1622 1623 struct wlfw_mlo_reconfig_info_resp_msg_v01 { 1624 struct qmi_response_type_v01 resp; 1625 }; 1626 #define WLFW_MLO_RECONFIG_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 1627 extern struct qmi_elem_info wlfw_mlo_reconfig_info_resp_msg_v01_ei[]; 1628 1629 struct wlfw_driver_async_data_ind_msg_v01 { 1630 u32 data_len; 1631 u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; 1632 u16 type; 1633 }; 1634 #define WLFW_DRIVER_ASYNC_DATA_IND_MSG_V01_MAX_MSG_LEN 6154 1635 extern struct qmi_elem_info wlfw_driver_async_data_ind_msg_v01_ei[]; 1636 1637 #endif 1638