1 /*
2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for
6 * any purpose with or without fee is hereby granted, provided that the
7 * above copyright notice and this permission notice appear in all
8 * copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17 * PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #ifndef _HAL_HW_INTERNAL_H_
21 #define _HAL_HW_INTERNAL_H_
22 #include "qdf_types.h"
23 #include "qdf_lock.h"
24 #include "qdf_mem.h"
25 #include "qdf_trace.h"
26 #include "rx_msdu_link.h"
27 #include "rx_reo_queue.h"
28 #include "rx_reo_queue_ext.h"
29 #include "wcss_seq_hwiobase.h"
30 #include "tlv_hdr.h"
31 #include "tlv_tag_def.h"
32 #include "reo_destination_ring.h"
33 #include "reo_entrance_ring.h"
34 #include "reo_get_queue_stats.h"
35 #include "reo_get_queue_stats_status.h"
36 #include "tcl_data_cmd.h"
37 #include "tcl_gse_cmd.h"
38 #include "tcl_status_ring.h"
39 #include "ce_src_desc.h"
40 #include "ce_stat_desc.h"
41 #include "wbm_link_descriptor_ring.h"
42 #include "wbm_buffer_ring.h"
43 #include "wbm_release_ring.h"
44 #include "rx_msdu_desc_info.h"
45 #include "rx_mpdu_start.h"
46 #include "rx_mpdu_end.h"
47 #include "rx_msdu_start.h"
48 #include "rx_msdu_end.h"
49 #include "rx_attention.h"
50 #include "rx_ppdu_start.h"
51 #include "rx_ppdu_start_user_info.h"
52 #include "rx_ppdu_end_user_stats.h"
53 #include "rx_ppdu_end_user_stats_ext.h"
54 #include "rx_mpdu_desc_info.h"
55 #include "rxpcu_ppdu_end_info.h"
56 #include "phyrx_he_sig_a_su.h"
57 #include "phyrx_he_sig_a_mu_dl.h"
58 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX)
59 #include "phyrx_he_sig_a_mu_ul.h"
60 #endif
61 #include "phyrx_he_sig_b1_mu.h"
62 #include "phyrx_he_sig_b2_mu.h"
63 #include "phyrx_he_sig_b2_ofdma.h"
64 #include "phyrx_l_sig_a.h"
65 #include "phyrx_l_sig_b.h"
66 #include "phyrx_vht_sig_a.h"
67 #include "phyrx_ht_sig.h"
68 #include "tx_msdu_extension.h"
69 #include "receive_rssi_info.h"
70 #include "phyrx_pkt_end.h"
71 #include "phyrx_rssi_legacy.h"
72 #include "wcss_version.h"
73 #include "rx_msdu_link.h"
74 #include "hal_internal.h"
75
76 #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_REO2SW1
77 #define HAL_SRNG_REO_ALTERNATE_SELECT 0x7
78 #define HAL_NON_QOS_TID 16
79
80 /* TODO: Check if the following can be provided directly by HW headers */
81 #define SRNG_LOOP_CNT_MASK REO_DESTINATION_RING_15_LOOPING_COUNT_MASK
82 #define SRNG_LOOP_CNT_LSB REO_DESTINATION_RING_15_LOOPING_COUNT_LSB
83
84 #define HAL_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
85 #define HAL_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
86
87 #define HAL_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
88 #define HAL_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
89
90 #define HAL_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR_SHFT 0x0
91 #define HAL_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff
92
93 #define HAL_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 0x8
94 #define HAL_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100
95
96 #define HAL_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
97 #define HAL_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
98
99 #define HAL_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 0x8
100 #define HAL_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00
101
102 #define HAL_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT 0x8
103 #define HAL_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK 0x0000ff00
104
105 #define HAL_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_SHFT 0x0
106 #define HAL_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_BMSK 0xff
107
108 #define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
109 #define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
110
111 #define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
112 #define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
113
114 #define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24
115 #define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000
116
117 #define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0
118 #define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff
119
120 #define HAL_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
121 #define HAL_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
122
123 #define HAL_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
124 #define HAL_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
125
126 #define HAL_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
127 #define HAL_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
128
129 /* HAL Macro to get the buffer info size */
130 #define HAL_RX_BUFFINFO_NUM_DWORDS NUM_OF_DWORDS_BUFFER_ADDR_INFO
131
132 #define HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS 100 /* milliseconds */
133 #define HAL_DEFAULT_VO_REO_TIMEOUT_MS 40 /* milliseconds */
134
135 #define HAL_DESC_SET_FIELD(_desc, _word, _fld, _value) do { \
136 ((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] &= \
137 ~(_word ## _ ## _fld ## _MASK); \
138 ((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] |= \
139 ((_value) << _word ## _ ## _fld ## _LSB); \
140 } while (0)
141
142 #define HAL_SM(_reg, _fld, _val) \
143 (((_val) << (_reg ## _ ## _fld ## _SHFT)) & \
144 (_reg ## _ ## _fld ## _BMSK))
145
146 #define HAL_MS(_reg, _fld, _val) \
147 (((_val) & (_reg ## _ ## _fld ## _BMSK)) >> \
148 (_reg ## _ ## _fld ## _SHFT))
149
150 #define HAL_REG_WRITE(_soc, _reg, _value) \
151 hal_write32_mb(_soc, (_reg), (_value))
152
153 /* Check register writing result */
154 #define HAL_REG_WRITE_CONFIRM(_soc, _reg, _value) \
155 hal_write32_mb_confirm(_soc, (_reg), (_value))
156
157 #define HAL_REG_WRITE_CONFIRM_RETRY(_soc, _reg, _value, _recovery) \
158 hal_write32_mb_confirm_retry(_soc, (_reg), (_value), (_recovery))
159
160 #define HAL_REG_READ(_soc, _offset) \
161 hal_read32_mb(_soc, (_offset))
162
163 #define HAL_CMEM_WRITE(_soc, _reg, _value) \
164 hal_write32_mb_cmem(_soc, (_reg), (_value))
165
166 #define HAL_CMEM_READ(_soc, _offset) \
167 hal_read32_mb_cmem(_soc, (_offset))
168
169 #define WBM_IDLE_DESC_LIST 1
170
171 /*
172 * Common SRNG register access macros:
173 * The SRNG registers are distributed across various UMAC and LMAC HW blocks,
174 * but the register group and format is exactly same for all rings, with some
175 * difference between producer rings (these are 'producer rings' with respect
176 * to HW and referred as 'destination rings' in SW) and consumer rings (these
177 * are 'consumer rings' with respect to HW and
178 * referred as 'source rings' in SW).
179 * The following macros provide uniform access to all SRNG rings.
180 */
181
182 /* SRNG registers are split among two groups R0 and R2 and following
183 * definitions identify the group to which each register belongs to
184 */
185 #define R0_INDEX 0
186 #define R2_INDEX 1
187
188 #define HWREG_INDEX(_reg_group) _reg_group ## _ ## INDEX
189
190 /* Registers in R0 group */
191 #define BASE_LSB_GROUP R0
192 #define BASE_MSB_GROUP R0
193 #define ID_GROUP R0
194 #define STATUS_GROUP R0
195 #define MISC_GROUP R0
196 #define MISC_1_GROUP R0
197 #define HP_ADDR_LSB_GROUP R0
198 #define HP_ADDR_MSB_GROUP R0
199 #define PRODUCER_INT_SETUP_GROUP R0
200 #define PRODUCER_INT2_SETUP_GROUP R0
201 #define PRODUCER_INT_STATUS_GROUP R0
202 #define PRODUCER_FULL_COUNTER_GROUP R0
203 #define MSI1_BASE_LSB_GROUP R0
204 #define MSI1_BASE_MSB_GROUP R0
205 #define MSI1_DATA_GROUP R0
206 #define MSI2_BASE_LSB_GROUP R0
207 #define MSI2_BASE_MSB_GROUP R0
208 #define MSI2_DATA_GROUP R0
209 #define HP_TP_SW_OFFSET_GROUP R0
210 #define TP_ADDR_LSB_GROUP R0
211 #define TP_ADDR_MSB_GROUP R0
212 #define CONSUMER_INT_SETUP_IX0_GROUP R0
213 #define CONSUMER_INT_SETUP_IX1_GROUP R0
214 #define CONSUMER_INT_STATUS_GROUP R0
215 #define CONSUMER_EMPTY_COUNTER_GROUP R0
216 #define CONSUMER_PREFETCH_TIMER_GROUP R0
217 #define CONSUMER_PREFETCH_STATUS_GROUP R0
218
219 /* Registers in R2 group */
220 #define HP_GROUP R2
221 #define TP_GROUP R2
222
223 /*
224 * Register definitions for all SRNG based rings are same, except few
225 * differences between source (HW consumer) and destination (HW producer)
226 * registers. Following macros definitions provide generic access to all
227 * SRNG based rings.
228 * For source rings, we will use the register/field definitions of SW2TCL1
229 * ring defined in the HW header file mac_tcl_reg_seq_hwioreg.h. To setup
230 * individual fields, SRNG_SM macros should be used with fields specified
231 * using SRNG_SRC_FLD(<register>, <field>), Register writes should be done
232 * using SRNG_SRC_REG_WRITE(<hal_srng>, <register>, <value>).
233 * Similarly for destination rings we will use definitions of REO2SW1 ring
234 * defined in the register reo_destination_ring.h. To setup individual
235 * fields SRNG_SM macros should be used with fields specified using
236 * SRNG_DST_FLD(<register>, <field>). Register writes should be done using
237 * SRNG_DST_REG_WRITE(<hal_srng>, <register>, <value>).
238 */
239
240 #define SRNG_DST_REG_OFFSET(_reg, _reg_group) \
241 HWIO_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg##_ADDR(0)
242
243 #define SRNG_SRC_REG_OFFSET(_reg, _reg_group) \
244 HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg ## _ADDR(0)
245
246 #define _SRNG_DST_FLD(_reg_group, _reg_fld) \
247 HAL_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg_fld
248 #define _SRNG_DST_HW_FLD(_reg_group, _reg_fld) \
249 HWIO_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg_fld
250 #define _SRNG_SRC_FLD(_reg_group, _reg_fld) \
251 HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg_fld
252
253 #define _SRNG_FLD(_reg_group, _reg_fld, _dir) \
254 _SRNG_ ## _dir ## _FLD(_reg_group, _reg_fld)
255 #define _SRNG_HW_FLD(_reg_group, _reg_fld, _dir) \
256 _SRNG_ ## _dir ## _HW_FLD(_reg_group, _reg_fld)
257
258 #define SRNG_DST_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, DST)
259 #define SRNG_DST_HW_FLD(_reg, _f) \
260 _SRNG_HW_FLD(_reg ## _GROUP, _reg ## _ ## _f, DST)
261 #define SRNG_SRC_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, SRC)
262
263 #define SRNG_SRC_R0_START_OFFSET SRNG_SRC_REG_OFFSET(BASE_LSB, R0)
264 #define SRNG_DST_R0_START_OFFSET SRNG_DST_REG_OFFSET(BASE_LSB, R0)
265
266 #define SRNG_SRC_R2_START_OFFSET SRNG_SRC_REG_OFFSET(HP, R2)
267 #define SRNG_DST_R2_START_OFFSET SRNG_DST_REG_OFFSET(HP, R2)
268
269 #define SRNG_SRC_START_OFFSET(_reg_group) \
270 SRNG_SRC_ ## _reg_group ## _START_OFFSET
271 #define SRNG_DST_START_OFFSET(_reg_group) \
272 SRNG_DST_ ## _reg_group ## _START_OFFSET
273 #define SRNG_REG_ADDR(_srng, _reg, _reg_group, _dir) \
274 ((_srng)->hwreg_base[HWREG_INDEX(_reg_group)] + \
275 ((_srng)->hal_soc->hal_hw_reg_offset[_dir ## _ ##_reg]))
276
277 #define CALCULATE_REG_OFFSET(_dir, _reg, _reg_group) \
278 (SRNG_ ## _dir ## _REG_OFFSET(_reg, _reg_group) - \
279 SRNG_ ## _dir ## _START_OFFSET(_reg_group))
280
281 #define REG_OFFSET(_dir, _reg) \
282 CALCULATE_REG_OFFSET(_dir, _reg, _reg ## _GROUP)
283
284 #define SRNG_DST_ADDR(_srng, _reg) \
285 SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, DST)
286
287 #define SRNG_SRC_ADDR(_srng, _reg) \
288 SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, SRC)
289
290 #define SRNG_REG_WRITE(_srng, _reg, _value, _dir) \
291 hal_write_address_32_mb(_srng->hal_soc,\
292 SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value), false)
293
294 #define SRNG_REG_WRITE_CONFIRM(_srng, _reg, _value, _dir) \
295 hal_write_address_32_mb(_srng->hal_soc,\
296 SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value), true)
297
298 #define SRNG_REG_READ(_srng, _reg, _dir) \
299 hal_read_address_32_mb(_srng->hal_soc, \
300 SRNG_ ## _dir ## _ADDR(_srng, _reg))
301
302 #define SRNG_SRC_REG_WRITE(_srng, _reg, _value) \
303 SRNG_REG_WRITE(_srng, _reg, _value, SRC)
304
305 #define SRNG_DST_REG_WRITE(_srng, _reg, _value) \
306 SRNG_REG_WRITE(_srng, _reg, _value, DST)
307
308 #define SRNG_DST_REG_WRITE_CONFIRM(_srng, _reg, _value) \
309 SRNG_REG_WRITE_CONFIRM(_srng, _reg, _value, DST)
310
311 #define SRNG_SRC_REG_READ(_srng, _reg) \
312 SRNG_REG_READ(_srng, _reg, SRC)
313
314 #define SRNG_DST_REG_READ(_srng, _reg) \
315 SRNG_REG_READ(_srng, _reg, DST)
316
317 #define _SRNG_FM(_reg_fld) _reg_fld ## _BMSK
318 #define _SRNG_FS(_reg_fld) _reg_fld ## _SHFT
319
320 #define SRNG_SM(_reg_fld, _val) \
321 (((_val) << _SRNG_FS(_reg_fld)) & _SRNG_FM(_reg_fld))
322
323 #define SRNG_MS(_reg_fld, _val) \
324 (((_val) & _SRNG_FM(_reg_fld)) >> _SRNG_FS(_reg_fld))
325
326 #define SRNG_MAX_SIZE_DWORDS \
327 (SRNG_MS(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 0xffffffff))
328
329 /*
330 * HW ring configuration table to identify hardware ring attributes like
331 * register addresses, number of rings, ring entry size etc., for each type
332 * of SRNG ring.
333 *
334 * Currently there is just one HW ring table, but there could be multiple
335 * configurations in future based on HW variants from the same wifi3.0 family
336 * and hence need to be attached with hal_soc based on HW type
337 */
338 #define HAL_SRNG_CONFIG(_hal_soc, _ring_type) \
339 (&_hal_soc->hw_srng_table[_ring_type])
340
341 /**
342 * hal_set_link_desc_addr() - Setup link descriptor in a buffer_addr_info
343 * HW structure
344 * @hal_soc_hdl: HAL soc handle
345 * @desc: Descriptor entry (from WBM_IDLE_LINK ring)
346 * @cookie: SW cookie for the buffer/descriptor
347 * @link_desc_paddr: Physical address of link descriptor entry
348 * @bm_id: idle link BM id
349 */
hal_set_link_desc_addr(hal_soc_handle_t hal_soc_hdl,void * desc,uint32_t cookie,qdf_dma_addr_t link_desc_paddr,uint8_t bm_id)350 static inline void hal_set_link_desc_addr(hal_soc_handle_t hal_soc_hdl,
351 void *desc, uint32_t cookie,
352 qdf_dma_addr_t link_desc_paddr,
353 uint8_t bm_id)
354 {
355 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
356
357 if ((!hal_soc) || (!hal_soc->ops)) {
358 hal_err("hal handle is NULL");
359 return;
360 }
361
362 if (hal_soc->ops->hal_set_link_desc_addr)
363 hal_soc->ops->hal_set_link_desc_addr(desc, cookie,
364 link_desc_paddr,
365 bm_id);
366 }
367
368 /**
369 * hal_get_reo_qdesc_size - Get size of reo queue descriptor
370 *
371 * @hal_soc_hdl: Opaque HAL SOC handle
372 * @ba_window_size: BlockAck window size
373 * @tid: TID number
374 *
375 */
376 static inline
hal_get_reo_qdesc_size(hal_soc_handle_t hal_soc_hdl,uint32_t ba_window_size,int tid)377 uint32_t hal_get_reo_qdesc_size(hal_soc_handle_t hal_soc_hdl,
378 uint32_t ba_window_size, int tid)
379 {
380 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
381
382 if (hal_soc->ops->hal_get_reo_qdesc_size)
383 return hal_soc->ops->hal_get_reo_qdesc_size(ba_window_size,
384 tid);
385
386 return sizeof(struct rx_reo_queue);
387 }
388
389 /**
390 * hal_get_rx_max_ba_window - Get RX max BA window size per target
391 * @hal_soc_hdl: Opaque HAL SOC handle
392 * @tid: TID number
393 *
394 * Return: Max RX BA window size
395 */
396 static inline
hal_get_rx_max_ba_window(hal_soc_handle_t hal_soc_hdl,int tid)397 uint16_t hal_get_rx_max_ba_window(hal_soc_handle_t hal_soc_hdl,
398 int tid)
399 {
400 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
401
402 return hal_soc->ops->hal_get_rx_max_ba_window(tid);
403 }
404
405 /**
406 * hal_get_idle_link_bm_id() - Get idle link BM id from chid_id
407 * @hal_soc_hdl: Opaque HAL SOC handle
408 * @chip_id: mlo chip_id
409 *
410 * Returns: RBM ID
411 */
412 static inline
hal_get_idle_link_bm_id(hal_soc_handle_t hal_soc_hdl,uint8_t chip_id)413 uint8_t hal_get_idle_link_bm_id(hal_soc_handle_t hal_soc_hdl,
414 uint8_t chip_id)
415 {
416 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
417
418 if (hal_soc->ops->hal_get_idle_link_bm_id)
419 return hal_soc->ops->hal_get_idle_link_bm_id(chip_id);
420
421 return WBM_IDLE_DESC_LIST;
422 }
423 #endif /* _HAL_HW_INTERNAL_H_ */
424