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Searched refs:xe_mmio_wait32 (Results 1 – 13 of 13) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/xe/compat-i915-headers/
Dintel_uncore.h100 return xe_mmio_wait32(__compat_uncore_to_gt(uncore), reg, mask, value, in intel_wait_for_register()
110 return xe_mmio_wait32(__compat_uncore_to_gt(uncore), reg, mask, value, in intel_wait_for_register_fw()
121 return xe_mmio_wait32(__compat_uncore_to_gt(uncore), reg, mask, value, in __intel_wait_for_register()
/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_device.c412 ret = xe_mmio_wait32(gt, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false); in xe_driver_flr()
423 ret = xe_mmio_wait32(gt, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false); in xe_driver_flr()
430 ret = xe_mmio_wait32(gt, GU_DEBUG, DRIVERFLR_STATUS, DRIVERFLR_STATUS, in xe_driver_flr()
858 if (xe_mmio_wait32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0, in xe_device_td_flush()
883 if (xe_mmio_wait32(gt, XE2_GLOBAL_INVAL, 0x1, 0x0, 500, NULL, true)) in xe_device_l2_flush()
Dxe_mmio.h26 int xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
Dxe_force_wake.c114 ret = xe_mmio_wait32(gt, domain->reg_ack, domain->val, wake ? domain->val : 0, in __domain_wait()
Dxe_pcode.c74 err = xe_mmio_wait32(mmio, PCODE_MAILBOX, PCODE_READY, 0, in __pcode_mailbox_rw()
Dxe_guc.c438 ret = xe_mmio_wait32(gt, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false); in xe_guc_reset()
962 ret = xe_mmio_wait32(gt, reply_reg, GUC_HXG_MSG_0_ORIGIN, in xe_guc_mmio_send_recv()
988 ret = xe_mmio_wait32(gt, reply_reg, resp_mask, resp_mask, in xe_guc_mmio_send_recv()
Dxe_huc.c271 ret = xe_mmio_wait32(gt, huc_auth_modes[type].reg, huc_auth_modes[type].val, in xe_huc_auth()
Dxe_mmio.c410 int xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us, in xe_mmio_wait32() function
Dxe_gt_mcr.c582 ret = xe_mmio_wait32(gt, STEER_SEMAPHORE, 0x1, 0x1, 10, NULL, in mcr_lock()
Dxe_gsc.c193 return xe_mmio_wait32(gt, HECI_FWSTS1(MTL_GSC_HECI1_BASE), in gsc_fw_wait()
Dxe_gt.c653 err = xe_mmio_wait32(gt, GDRST, GRDOM_FULL, 0, 5000, NULL, false); in do_gt_reset()
Dxe_uc_fw.c837 ret = xe_mmio_wait32(gt, DMA_CTRL, START_DMA, 0, 100000, &dma_ctrl, in uc_fw_xfer()
Dxe_oa.c453 if (xe_mmio_wait32(stream->gt, __oa_regs(stream)->oa_ctrl, in xe_oa_disable()
461 if (xe_mmio_wait32(stream->gt, OA_TLB_INV_CR, 1, 0, 50000, NULL, false)) in xe_oa_disable()