Searched refs:xe_mmio_rmw32 (Results 1 – 10 of 10) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/xe/ |
| D | xe_mmio.h | 21 u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr, u32 set);
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| D | xe_hwmon.c | 204 reg_val = xe_mmio_rmw32(mmio, rapl_limit, PKG_PWR_LIM_1_EN, 0); in xe_hwmon_power_max_write()
216 reg_val = xe_mmio_rmw32(mmio, rapl_limit, PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val); in xe_hwmon_power_max_write()
383 r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, sensor_index), in xe_hwmon_power_max_interval_store()
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| D | xe_gsc.c | 584 xe_mmio_rmw32(gt, HECI_H_GS1(MTL_GSC_HECI2_BASE), gs1_clr, gs1_set); in xe_gsc_wa_14015076503()
588 xe_mmio_rmw32(gt, HECI_H_CSR(MTL_GSC_HECI2_BASE), in xe_gsc_wa_14015076503()
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| D | xe_mmio.c | 257 u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr, u32 set) in xe_mmio_rmw32() function
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| D | xe_guc.c | 481 xe_mmio_rmw32(gt, PMINTRMSK, ARAT_EXPIRED_INTRMSK, 0); in guc_prepare_xfer()
854 xe_mmio_rmw32(gt, GUC_SG_INTR_MASK, events, 0); in guc_enable_irq()
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| D | xe_gsc_proxy.c | 81 xe_mmio_rmw32(gt, HECI_H_CSR(MTL_GSC_HECI2_BASE), clr, set); in __gsc_proxy_irq_rmw()
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| D | xe_oa.c | 484 stream->oa_status = xe_mmio_rmw32(stream->gt, __oa_regs(stream)->oa_status, in __xe_oa_read()
809 xe_mmio_rmw32(stream->gt, RPM_CONFIG1, GT_NOA_ENABLE, 0); in xe_oa_disable_metric_set()
815 xe_mmio_rmw32(stream->gt, XELPMP_SQCNT1, sqcnt1, 0); in xe_oa_disable_metric_set()
988 xe_mmio_rmw32(stream->gt, XELPMP_SQCNT1, 0, sqcnt1); in xe_oa_enable_metric_set()
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| D | xe_wa.c | 900 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); in xe_wa_apply_tile_workarounds()
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| D | xe_device.c | 420 xe_mmio_rmw32(gt, GU_CNTL, 0, DRIVERFLR); in xe_driver_flr()
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| /linux-6.12.1/drivers/gpu/drm/xe/compat-i915-headers/ |
| D | intel_uncore.h | 91 return xe_mmio_rmw32(__compat_uncore_to_gt(uncore), reg, clear, set); in intel_uncore_rmw()
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