Searched refs:wcl_cs_reg (Results 1 – 3 of 3) sorted by relevance
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
D | gfx_v9_4_3.c | 3423 uint32_t wcl_cs_reg; in gfx_v9_4_3_emit_wave_limit_cs() local 3430 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); in gfx_v9_4_3_emit_wave_limit_cs() 3433 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); in gfx_v9_4_3_emit_wave_limit_cs() 3436 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); in gfx_v9_4_3_emit_wave_limit_cs() 3439 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); in gfx_v9_4_3_emit_wave_limit_cs() 3446 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v9_4_3_emit_wave_limit_cs()
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D | gfx_v8_0.c | 6836 uint32_t wcl_cs_reg; in gfx_v8_0_emit_wave_limit_cs() local 6842 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS0; in gfx_v8_0_emit_wave_limit_cs() 6845 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS1; in gfx_v8_0_emit_wave_limit_cs() 6848 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS2; in gfx_v8_0_emit_wave_limit_cs() 6851 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS3; in gfx_v8_0_emit_wave_limit_cs() 6858 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v8_0_emit_wave_limit_cs()
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D | gfx_v9_0.c | 7114 uint32_t wcl_cs_reg; in gfx_v9_0_emit_wave_limit_cs() local 7121 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS0); in gfx_v9_0_emit_wave_limit_cs() 7124 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS1); in gfx_v9_0_emit_wave_limit_cs() 7127 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS2); in gfx_v9_0_emit_wave_limit_cs() 7130 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS3); in gfx_v9_0_emit_wave_limit_cs() 7137 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v9_0_emit_wave_limit_cs()
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