Searched refs:wb_info (Results 1 – 11 of 11) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| D | dcn30_hwseq.c | 411 struct dc_writeback_info *wb_info, in dcn30_set_writeback() argument
417 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); in dcn30_set_writeback()
418 ASSERT(wb_info->wb_enabled); in dcn30_set_writeback()
419 ASSERT(wb_info->mpcc_inst >= 0); in dcn30_set_writeback()
420 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
421 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn30_set_writeback()
422 mcif_buf_params = &wb_info->mcif_buf_params; in dcn30_set_writeback()
426 wb_info->dwb_pipe_inst, wb_info->mpcc_inst); in dcn30_set_writeback()
428 mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height); in dcn30_set_writeback()
429 …mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info-… in dcn30_set_writeback()
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| D | dcn30_hwseq.h | 40 struct dc_writeback_info *wb_info,
44 struct dc_writeback_info *wb_info,
53 struct dc_writeback_info *wb_info);
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | dcn30_fpu.c | 278 struct dc_writeback_info *wb_info = &stream->writeback_info[j]; in dcn30_fpu_populate_dml_writeback_from_context() local
280 if (wb_info->wb_enabled && wb_info->writeback_source_plane && in dcn30_fpu_populate_dml_writeback_from_context()
281 (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) { in dcn30_fpu_populate_dml_writeback_from_context()
284 dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ? in dcn30_fpu_populate_dml_writeback_from_context()
285 wb_info->dwb_params.cnv_params.crop_height : in dcn30_fpu_populate_dml_writeback_from_context()
286 wb_info->dwb_params.cnv_params.src_height; in dcn30_fpu_populate_dml_writeback_from_context()
287 dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ? in dcn30_fpu_populate_dml_writeback_from_context()
288 wb_info->dwb_params.cnv_params.crop_width : in dcn30_fpu_populate_dml_writeback_from_context()
289 wb_info->dwb_params.cnv_params.src_width; in dcn30_fpu_populate_dml_writeback_from_context()
290 dout_wb.wb_dst_width = wb_info->dwb_params.dest_width; in dcn30_fpu_populate_dml_writeback_from_context()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_stream.c | 458 struct dc_writeback_info *wb_info) in dc_stream_add_writeback() argument
469 if (wb_info == NULL) { in dc_stream_add_writeback()
474 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) { in dc_stream_add_writeback()
481 wb_info->dwb_params.out_transfer_func = &stream->out_transfer_func; in dc_stream_add_writeback()
483 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
491 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) { in dc_stream_add_writeback()
492 stream->writeback_info[i] = *wb_info; in dc_stream_add_writeback()
499 stream->writeback_info[stream->num_wb_info++] = *wb_info; in dc_stream_add_writeback()
504 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
516 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.c | 999 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; in dcn20_populate_dml_writeback_from_context() local
1005 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; in dcn20_populate_dml_writeback_from_context()
1007 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; in dcn20_populate_dml_writeback_from_context()
1008 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; in dcn20_populate_dml_writeback_from_context()
1009 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; in dcn20_populate_dml_writeback_from_context()
1010 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; in dcn20_populate_dml_writeback_from_context()
1013 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; in dcn20_populate_dml_writeback_from_context()
1014 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c; in dcn20_populate_dml_writeback_from_context()
1017 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) { in dcn20_populate_dml_writeback_from_context()
1018 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) in dcn20_populate_dml_writeback_from_context()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/ |
| D | dml2_translation_helper.c | 1206 const struct dc_writeback_info *wb_info = &in->writeback_info[i]; in populate_dml_writeback_cfg_from_stream_state() local
1208 if (wb_info->wb_enabled) { in populate_dml_writeback_cfg_from_stream_state()
1209 out->WritebackEnable[location] = wb_info->wb_enabled; in populate_dml_writeback_cfg_from_stream_state()
1210 out->ActiveWritebacksPerSurface[location] = wb_info->dwb_params.cnv_params.src_width; in populate_dml_writeback_cfg_from_stream_state()
1211 out->WritebackDestinationWidth[location] = wb_info->dwb_params.dest_width; in populate_dml_writeback_cfg_from_stream_state()
1212 out->WritebackDestinationHeight[location] = wb_info->dwb_params.dest_height; in populate_dml_writeback_cfg_from_stream_state()
1214 out->WritebackSourceWidth[location] = wb_info->dwb_params.cnv_params.crop_en ? in populate_dml_writeback_cfg_from_stream_state()
1215 wb_info->dwb_params.cnv_params.crop_width : in populate_dml_writeback_cfg_from_stream_state()
1216 wb_info->dwb_params.cnv_params.src_width; in populate_dml_writeback_cfg_from_stream_state()
1218 out->WritebackSourceHeight[location] = wb_info->dwb_params.cnv_params.crop_en ? in populate_dml_writeback_cfg_from_stream_state()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/ |
| D | hw_sequencer.h | 326 struct dc_writeback_info *wb_info,
329 struct dc_writeback_info *wb_info,
336 struct dc_writeback_info *wb_info);
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/ |
| D | dc_stream.h | 433 struct dc_writeback_info *wb_info);
449 struct dc_writeback_info *wb_info);
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| /linux-6.12.1/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm.c | 9630 struct dc_writeback_info *wb_info; in dm_set_writeback() local
9635 wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL); in dm_set_writeback()
9636 if (!wb_info) { in dm_set_writeback()
9644 kfree(wb_info); in dm_set_writeback()
9651 kfree(wb_info); in dm_set_writeback()
9663 wb_info->wb_enabled = true; in dm_set_writeback()
9665 wb_info->dwb_pipe_inst = 0; in dm_set_writeback()
9666 wb_info->dwb_params.dwbscl_black_color = 0; in dm_set_writeback()
9667 wb_info->dwb_params.hdr_mult = 0x1F000; in dm_set_writeback()
9668 wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS; in dm_set_writeback()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| D | dcn20_hwseq.h | 116 struct dc_writeback_info *wb_info,
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| D | dcn20_hwseq.c | 2500 struct dc_writeback_info *wb_info, in dcn20_enable_writeback() argument
2507 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); in dcn20_enable_writeback()
2508 ASSERT(wb_info->wb_enabled); in dcn20_enable_writeback()
2509 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn20_enable_writeback()
2510 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn20_enable_writeback()
2514 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); in dcn20_enable_writeback()
2516 …mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_heigh… in dcn20_enable_writeback()
2517 …mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info-… in dcn20_enable_writeback()
2521 dwb->funcs->enable(dwb, &wb_info->dwb_params); in dcn20_enable_writeback()
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