| /linux-6.12.1/sound/pci/emu10k1/ |
| D | emu10k1.c | 75 struct snd_seq_device *wave = NULL; in snd_card_emu10k1_probe() local
150 sizeof(struct snd_emu10k1_synth_arg), &wave) < 0 || in snd_card_emu10k1_probe()
151 wave == NULL) { in snd_card_emu10k1_probe()
156 arg = SNDRV_SEQ_DEVICE_ARGPTR(wave); in snd_card_emu10k1_probe()
157 strcpy(wave->name, "Emu-10k1 Synth"); in snd_card_emu10k1_probe()
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| /linux-6.12.1/sound/pci/ |
| D | ad1889.c | 90 struct ad1889_register_state wave; member
190 chip->wave.reg = reg; in ad1889_channel_reset()
358 chip->wave.size = size; in snd_ad1889_playback_prepare()
359 chip->wave.reg = reg; in snd_ad1889_playback_prepare()
360 chip->wave.addr = rt->dma_addr; in snd_ad1889_playback_prepare()
362 ad1889_writew(chip, AD_DS_WSMC, chip->wave.reg); in snd_ad1889_playback_prepare()
368 ad1889_load_wave_buffer_address(chip, chip->wave.addr); in snd_ad1889_playback_prepare()
379 chip->wave.addr, count, size, reg, rt->rate); in snd_ad1889_playback_prepare()
460 chip->wave.reg = wsmc; in snd_ad1889_playback_trigger()
516 if (unlikely(!(chip->wave.reg & AD_DS_WSMC_WAEN))) in snd_ad1889_playback_pointer()
[all …]
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| /linux-6.12.1/sound/pci/au88x0/ |
| D | au88x0.c | 267 sizeof(snd_vortex_synth_arg_t), &wave) < 0 in __snd_vortex_probe()
268 || wave == NULL) { in __snd_vortex_probe()
273 arg = SNDRV_SEQ_DEVICE_ARGPTR(wave); in __snd_vortex_probe()
274 strcpy(wave->name, "Aureal Synth"); in __snd_vortex_probe()
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v9_4_2.c | 422 uint32_t se, cu, simd, wave; in gfx_v9_4_2_log_wave_assignment() local
439 for (wave = 0; wave < WAVE_ID_MAX; wave++) { in gfx_v9_4_2_log_wave_assignment()
456 uint32_t se, cu, simd, wave; in gfx_v9_4_2_wait_for_waves_assigned() local
468 for (wave = 0; wave < WAVE_ID_MAX; wave++) { in gfx_v9_4_2_wait_for_waves_assigned()
469 if (((1 << wave) & mask) && in gfx_v9_4_2_wait_for_waves_assigned()
1804 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
1807 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
1818 uint32_t i, simd, wave; in gfx_v9_4_2_log_cu_timeout_status() local
1830 wave = i % cu_info->max_waves_per_simd; in gfx_v9_4_2_log_cu_timeout_status()
1832 wave_status = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_2_log_cu_timeout_status()
[all …]
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| D | gfx_v6_0.c | 2945 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
2948 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
2956 uint32_t wave, uint32_t thread, in wave_read_regs() argument
2960 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
2970 …data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int… in gfx_v6_0_read_wave_data() argument
2974 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v6_0_read_wave_data()
2975 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v6_0_read_wave_data()
2976 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v6_0_read_wave_data()
2977 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v6_0_read_wave_data()
2978 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v6_0_read_wave_data()
[all …]
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| D | gfx_v7_0.c | 4049 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
4052 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
4060 uint32_t wave, uint32_t thread, in wave_read_regs() argument
4064 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
4074 …data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int… in gfx_v7_0_read_wave_data() argument
4078 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v7_0_read_wave_data()
4079 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v7_0_read_wave_data()
4080 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v7_0_read_wave_data()
4081 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v7_0_read_wave_data()
4082 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v7_0_read_wave_data()
[all …]
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| D | amdgpu_umr.h | 50 u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id; member
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| D | gfx_v12_0.c | 776 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) in wave_read_ind() argument
779 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
784 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, in wave_read_regs() argument
789 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
799 uint32_t simd, uint32_t wave, in gfx_v12_0_read_wave_data() argument
809 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); in gfx_v12_0_read_wave_data()
810 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); in gfx_v12_0_read_wave_data()
811 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); in gfx_v12_0_read_wave_data()
812 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); in gfx_v12_0_read_wave_data()
813 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); in gfx_v12_0_read_wave_data()
[all …]
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| D | amdgpu_debugfs.c | 434 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); in amdgpu_debugfs_gprwave_read()
439 …adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread,… in amdgpu_debugfs_gprwave_read()
442 …adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, dat… in amdgpu_debugfs_gprwave_read()
1061 uint32_t offset, se, sh, cu, wave, simd, data[32]; in amdgpu_debugfs_wave_read() local
1071 wave = (*pos & GENMASK_ULL(36, 31)) >> 31; in amdgpu_debugfs_wave_read()
1092 adev->gfx.funcs->read_wave_data(adev, 0, simd, wave, data, &x); in amdgpu_debugfs_wave_read()
1153 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; in amdgpu_debugfs_gpr_read() local
1163 wave = (*pos & GENMASK_ULL(43, 36)) >> 36; in amdgpu_debugfs_gpr_read()
1186 adev->gfx.funcs->read_wave_vgprs(adev, 0, simd, wave, thread, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
1189 adev->gfx.funcs->read_wave_sgprs(adev, 0, simd, wave, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
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| D | amdgpu_gfx.h | 293 uint32_t wave, uint32_t *dst, int *no_fields);
295 uint32_t wave, uint32_t thread, uint32_t start,
298 uint32_t wave, uint32_t start, uint32_t size,
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| D | gfx_v9_4_3.c | 719 …ad_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) in wave_read_ind() argument
722 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
730 uint32_t wave, uint32_t thread, in wave_read_regs() argument
734 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
745 uint32_t xcc_id, uint32_t simd, uint32_t wave, in gfx_v9_4_3_read_wave_data() argument
750 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_3_read_wave_data()
751 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_4_3_read_wave_data()
752 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_4_3_read_wave_data()
753 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_4_3_read_wave_data()
754 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_4_3_read_wave_data()
[all …]
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| D | gfx_v8_0.c | 5189 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
5192 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
5200 uint32_t wave, uint32_t thread, in wave_read_regs() argument
5204 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
5214 …data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int… in gfx_v8_0_read_wave_data() argument
5218 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v8_0_read_wave_data()
5219 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v8_0_read_wave_data()
5220 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v8_0_read_wave_data()
5221 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v8_0_read_wave_data()
5222 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v8_0_read_wave_data()
[all …]
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| D | gfx_v11_0.c | 950 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) in wave_read_ind() argument
953 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
958 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, in wave_read_regs() argument
963 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
971 …data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int… in gfx_v11_0_read_wave_data() argument
980 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); in gfx_v11_0_read_wave_data()
981 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); in gfx_v11_0_read_wave_data()
982 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); in gfx_v11_0_read_wave_data()
983 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); in gfx_v11_0_read_wave_data()
984 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); in gfx_v11_0_read_wave_data()
[all …]
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| D | gfx_v9_0.c | 1918 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
1921 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
1929 uint32_t wave, uint32_t thread, in wave_read_regs() argument
1933 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
1943 …data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int… in gfx_v9_0_read_wave_data() argument
1947 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_0_read_wave_data()
1948 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_0_read_wave_data()
1949 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_0_read_wave_data()
1950 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_0_read_wave_data()
1951 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_0_read_wave_data()
[all …]
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| D | gfx_v10_0.c | 4411 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) in wave_read_ind() argument
4414 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
4419 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, in wave_read_regs() argument
4424 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
4432 …data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int… in gfx_v10_0_read_wave_data() argument
4442 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); in gfx_v10_0_read_wave_data()
4443 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); in gfx_v10_0_read_wave_data()
4444 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); in gfx_v10_0_read_wave_data()
4445 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); in gfx_v10_0_read_wave_data()
4446 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); in gfx_v10_0_read_wave_data()
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ti/davinci/ |
| D | pll.txt | 18 - ti,clkmode-square-wave: Indicates that the board is supplying a square
19 wave input on the OSCIN pin instead of using a crystal oscillator.
61 ti,clkmode-square-wave;
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| /linux-6.12.1/drivers/gpu/ipu-v3/ |
| D | ipu-dc.c | 120 int map, int wave, int glue, int sync, int stop) in dc_write_tmpl() argument
129 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000); in dc_write_tmpl()
132 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000); in dc_write_tmpl()
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | nvidia,tegra124-dfll.txt | 56 - nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.
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| /linux-6.12.1/Documentation/virt/kvm/x86/ |
| D | timekeeping.rst | 103 This generates a high / low square wave. The count
112 which generates sine-like tones by low-pass filtering the square wave output.
253 bit 3 = Square wave interrupt enable
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| /linux-6.12.1/Documentation/driver-api/media/drivers/ |
| D | vidtv.rst | 34 Elementary Stream, which in turn contains a SMPTE 302m encoded sine-wave.
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| /linux-6.12.1/Documentation/ABI/testing/ |
| D | sysfs-bus-counter | 115 square wave mode:
|