| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_crt.c | 704 u32 vblank, vblank_start, vblank_end; in intel_crt_load_detect() local
722 vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1; in intel_crt_load_detect()
753 if (vblank_start <= vactive && vblank_end >= vtotal) { in intel_crt_load_detect()
762 VBLANK_END(vblank_end - 1)); in intel_crt_load_detect()
766 if (vblank_start - vactive >= vtotal - vblank_end) in intel_crt_load_detect()
769 vsample = (vtotal + vblank_end) >> 1; in intel_crt_load_detect()
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| D | intel_vblank.c | 582 int vblank_end = mode->crtc_vblank_end; in intel_mode_vblank_end() local
585 vblank_end /= 2; in intel_mode_vblank_end()
587 return vblank_end; in intel_mode_vblank_end()
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| D | intel_vbt_defs.h | 627 u16 vblank_end; member
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.c | 852 unsigned int vblank_end = dst->vblank_end; in dml_rq_dlg_get_dlg_params() local
974 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml_rq_dlg_get_dlg_params()
1074 <= vblank_end / 2.0) in dml_rq_dlg_get_dlg_params()
1081 <= vblank_end) in dml_rq_dlg_get_dlg_params()
1097 vblank_end); in dml_rq_dlg_get_dlg_params()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_rq_dlg_calc_20.c | 806 unsigned int vblank_end = dst->vblank_end; in dml20_rq_dlg_get_dlg_params() local
928 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml20_rq_dlg_get_dlg_params()
1034 <= vblank_end / 2.0) in dml20_rq_dlg_get_dlg_params()
1041 <= vblank_end) in dml20_rq_dlg_get_dlg_params()
1056 vblank_end); in dml20_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_20v2.c | 806 unsigned int vblank_end = dst->vblank_end; in dml20v2_rq_dlg_get_dlg_params() local
928 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml20v2_rq_dlg_get_dlg_params()
1035 <= vblank_end / 2.0) in dml20v2_rq_dlg_get_dlg_params()
1042 <= vblank_end) in dml20v2_rq_dlg_get_dlg_params()
1057 vblank_end); in dml20v2_rq_dlg_get_dlg_params()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | display_rq_dlg_calc_32.c | 232 unsigned int vblank_end = dst->vblank_end; in dml32_rq_dlg_get_dlg_reg() local
277 dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml32_rq_dlg_get_dlg_reg()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_rq_dlg_calc_30.c | 918 unsigned int vblank_end = dst->vblank_end; in dml_rq_dlg_get_dlg_params() local
1045 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml_rq_dlg_get_dlg_params()
1135 <= vblank_end / 2.0) in dml_rq_dlg_get_dlg_params()
1142 <= vblank_end) in dml_rq_dlg_get_dlg_params()
1157 vblank_end); in dml_rq_dlg_get_dlg_params()
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| /linux-6.12.1/drivers/video/fbdev/ |
| D | gbefb.c | 522 timing->vblank_end = timing->vtotal; in compute_gbe_timing()
561 SET_GBE_FIELD(VT_VBLANK, VBLANK_OFF, val, timing->vblank_end); in gbe_set_timing_info()
573 SET_GBE_FIELD(VT_VCMAP, VCMAP_OFF, val, timing->vblank_end); in gbe_set_timing_info()
581 temp = timing->vblank_start - timing->vblank_end - 1; in gbe_set_timing_info()
625 SET_GBE_FIELD(VT_VPIXEN, VPIXEN_ON, val, timing->vblank_end); in gbe_set_timing_info()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | display_rq_dlg_calc_31.c | 880 unsigned int vblank_end = dst->vblank_end; in dml_rq_dlg_get_dlg_params() local
981 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml_rq_dlg_get_dlg_params()
1032 …art / 2.0 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end / 2.0) in dml_rq_dlg_get_dlg_params()
1037 …(vstartup_start - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end) in dml_rq_dlg_get_dlg_params()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/ |
| D | dml2_utils.c | 242 unsigned int hactive, vactive, hblank_start, vblank_start, hblank_end, vblank_end; in populate_pipe_ctx_dlg_params_from_dml() local
251 vblank_end = vblank_start - timing->v_addressable - timing->v_border_top - timing->v_border_bottom; in populate_pipe_ctx_dlg_params_from_dml()
265 pipe_ctx->pipe_dlg_param.vblank_end = vblank_end; in populate_pipe_ctx_dlg_params_from_dml()
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| D | dml_display_rq_dlg_calc.c | 214 dml_uint_t vblank_end = timing->VBlankEnd[plane_idx]; in dml_rq_dlg_get_dlg_reg() local
320 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml_rq_dlg_get_dlg_reg()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| D | display_rq_dlg_calc_314.c | 965 unsigned int vblank_end = dst->vblank_end; in dml_rq_dlg_get_dlg_params() local
1066 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml_rq_dlg_get_dlg_params()
1119 …art / 2.0 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end / 2.0) in dml_rq_dlg_get_dlg_params()
1124 …(vstartup_start - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end) in dml_rq_dlg_get_dlg_params()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/ |
| D | dml1_display_rq_dlg_calc.c | 1013 unsigned int vblank_end = e2e_pipe_param->pipe.dest.vblank_end; in dml1_rq_dlg_get_dlg_params() local
1160 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; /* 15 bits */ in dml1_rq_dlg_get_dlg_params()
1262 vblank_end); in dml1_rq_dlg_get_dlg_params()
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| D | display_mode_structs.h | 515 unsigned int vblank_end; member
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| D | display_mode_lib.c | 228 dml_print("DML PARAMS: vblank_end = %d\n", pipe_dest->vblank_end); in dml_log_pipe_params()
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| /linux-6.12.1/include/video/ |
| D | gbe.h | 298 short vblank_end; /* Vertical blank end */ member
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| D | dml21_translation_helper.c | 1109 unsigned int hactive, vactive, hblank_start, vblank_start, hblank_end, vblank_end; in dml21_populate_pipe_ctx_dlg_params() local
1119 vblank_end = vblank_start - timing->v_addressable - timing->v_border_top - timing->v_border_bottom; in dml21_populate_pipe_ctx_dlg_params()
1139 pipe_ctx->pipe_dlg_param.vblank_end = vblank_end; in dml21_populate_pipe_ctx_dlg_params()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| D | dcn_calcs.c | 440 input->dest.vblank_end = input->dest.vblank_start in pipe_ctx_to_e2e_pipe_params()
1232 pipe->pipe_dlg_param.vblank_end = asic_blank_end; in dcn_validate_bandwidth()
1258 hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end; in dcn_validate_bandwidth()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dmub/inc/ |
| D | dmub_cmd.h | 1602 uint16_t vblank_end; member
1788 uint16_t vblank_end; member
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| D | dcn401_hubp.c | 160 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { in hubp401_vready_at_or_After_vsync()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| D | dcn10_hubp.c | 132 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { in hubp1_vready_workaround()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| D | dml2_core_shared_types.h | 1393 unsigned int vblank_end; member
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| /linux-6.12.1/drivers/gpu/drm/i915/ |
| D | i915_reg.h | 1095 #define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end)) argument
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn20/ |
| D | dcn20_hubp.c | 188 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { in hubp2_vready_at_or_After_vsync()
|