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Searched refs:vba (Results 1 – 25 of 31) sorted by relevance

12

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_mode_vba_20.c237 mode_lib->vba.FabricAndDRAMBandwidth = dml_min( in dml20_recalculate()
238 mode_lib->vba.DRAMSpeed * mode_lib->vba.NumberOfChannels * mode_lib->vba.DRAMChannelWidth, in dml20_recalculate()
239 mode_lib->vba.FabricClock * mode_lib->vba.FabricDatapathToDCNDataReturn) / 1000.0; in dml20_recalculate()
255 > mode_lib->vba.DCFCLK * mode_lib->vba.ReturnBusWidth / 4.0) in adjust_ReturnBW()
261 - mode_lib->vba.UrgentLatencyPixelDataOnly in adjust_ReturnBW()
262 / ((mode_lib->vba.ROBBufferSizeInKByte in adjust_ReturnBW()
263 - mode_lib->vba.PixelChunkSizeInKByte) in adjust_ReturnBW()
266 - mode_lib->vba.DCFCLK in adjust_ReturnBW()
267 * mode_lib->vba.ReturnBusWidth in adjust_ReturnBW()
269 + mode_lib->vba.UrgentLatencyPixelDataOnly)); in adjust_ReturnBW()
[all …]
Ddisplay_mode_vba_20v2.c261 mode_lib->vba.FabricAndDRAMBandwidth = dml_min( in dml20v2_recalculate()
262 mode_lib->vba.DRAMSpeed * mode_lib->vba.NumberOfChannels * mode_lib->vba.DRAMChannelWidth, in dml20v2_recalculate()
263 mode_lib->vba.FabricClock * mode_lib->vba.FabricDatapathToDCNDataReturn) / 1000.0; in dml20v2_recalculate()
279 > mode_lib->vba.DCFCLK * mode_lib->vba.ReturnBusWidth / 4.0) in adjust_ReturnBW()
285 - mode_lib->vba.UrgentLatencyPixelDataOnly in adjust_ReturnBW()
286 / ((mode_lib->vba.ROBBufferSizeInKByte in adjust_ReturnBW()
287 - mode_lib->vba.PixelChunkSizeInKByte) in adjust_ReturnBW()
290 - mode_lib->vba.DCFCLK in adjust_ReturnBW()
291 * mode_lib->vba.ReturnBusWidth in adjust_ReturnBW()
293 + mode_lib->vba.UrgentLatencyPixelDataOnly)); in adjust_ReturnBW()
[all …]
Ddcn20_fpu.c1086 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in decide_zstate_support()
1096 if (is_pwrseq0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0) in decide_zstate_support()
1154 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn20_calculate_dlg_params()
1155 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; in dcn20_calculate_dlg_params()
1156 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn20_calculate_dlg_params()
1157 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; in dcn20_calculate_dlg_params()
1162 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; in dcn20_calculate_dlg_params()
1163 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; in dcn20_calculate_dlg_params()
1165 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] in dcn20_calculate_dlg_params()
1226 …bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] … in dcn20_calculate_dlg_params()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn32/
Ddisplay_mode_vba_32.c41 dml32_CalculateMaxDETAndMinCompressedBufferSize(mode_lib->vba.ConfigReturnBufferSizeInKByte, in dml32_recalculate()
42 mode_lib->vba.ROBBufferSizeInKByte, in dml32_recalculate()
48 &mode_lib->vba.MaxTotalDETInKByte, &mode_lib->vba.nomDETInKByte, in dml32_recalculate()
49 &mode_lib->vba.MinCompressedBufferSizeInKByte); in dml32_recalculate()
61 struct vba_vars_st *v = &mode_lib->vba; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
76 dml_print("DML::%s: mode_lib->vba.PrefetchMode = %d\n", __func__, mode_lib->vba.PrefetchMode); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
77 …dml_print("DML::%s: mode_lib->vba.ImmediateFlipSupport = %d\n", __func__, mode_lib->vba.ImmediateF… in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
78 dml_print("DML::%s: mode_lib->vba.VoltageLevel = %d\n", __func__, mode_lib->vba.VoltageLevel); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
85 for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
86 if (mode_lib->vba.WritebackEnable[k]) { in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
[all …]
Ddcn32_fpu.c282 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() local
284 …ock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context->bw_ctx… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
290 …vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_suppor… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
296 if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
298 …vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_suppor… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
300 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
301 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
478 unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel; in dcn32_set_phantom_stream_timing()
479 …unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcCo… in dcn32_set_phantom_stream_timing()
480 unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel]; in dcn32_set_phantom_stream_timing()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_mode_vba.c57 bool need_recalculate = memcmp(&mode_lib->soc, &mode_lib->vba.soc, sizeof(mode_lib->vba.soc)) != 0 in dml_get_voltage_level()
58 || memcmp(&mode_lib->ip, &mode_lib->vba.ip, sizeof(mode_lib->vba.ip)) != 0 in dml_get_voltage_level()
59 || num_pipes != mode_lib->vba.cache_num_pipes in dml_get_voltage_level()
60 || memcmp(pipes, mode_lib->vba.cache_pipes, in dml_get_voltage_level()
63 mode_lib->vba.soc = mode_lib->soc; in dml_get_voltage_level()
64 mode_lib->vba.ip = mode_lib->ip; in dml_get_voltage_level()
65 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes); in dml_get_voltage_level()
66 mode_lib->vba.cache_num_pipes = num_pipes; in dml_get_voltage_level()
79 return mode_lib->vba.VoltageLevel; in dml_get_voltage_level()
88 dml_get_attr_func(clk_dcf_deepsleep, mode_lib->vba.DCFCLKDeepSleep);
[all …]
Ddisplay_mode_lib.c291 for (i = mode_lib->vba.soc.num_states; i >= 0; i--) { in dml_log_mode_support_params()
294 …dml_print("DML SUPPORT: Mode Supported : %s\n", mode_lib->vba.ModeSupport[i][0] ?… in dml_log_mode_support_params()
295 …dml_print("DML SUPPORT: Mode Supported (pipe split) : %s\n", mode_lib->vba.ModeSupport[i][1] ?… in dml_log_mode_support_params()
296 …dml_print("DML SUPPORT: Scale Ratio And Taps : %s\n", mode_lib->vba.ScaleRatioA… in dml_log_mode_support_params()
297 …dml_print("DML SUPPORT: Source Format Pixel And Scan : %s\n", mode_lib->vba.SourceForma… in dml_log_mode_support_params()
298 … : [%s, %s]\n", mode_lib->vba.ViewportSizeSupport[i][0] ? "Supported" : "NOT Supported… in dml_log_mode_support_params()
299 …dml_print("DML SUPPORT: DIO Support : %s\n", mode_lib->vba.DIOSupport[… in dml_log_mode_support_params()
300 …dml_print("DML SUPPORT: ODM Combine 4To1 Support Check : %s\n", mode_lib->vba.ODMCombine4… in dml_log_mode_support_params()
301 …dml_print("DML SUPPORT: DSC Units : %s\n", mode_lib->vba.NotEnoughDS… in dml_log_mode_support_params()
302 …dml_print("DML SUPPORT: DSCCLK Required : %s\n", mode_lib->vba.DSCCLKRequi… in dml_log_mode_support_params()
[all …]
Ddisplay_mode_lib.h89 struct vba_vars_st vba; member
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_mode_vba_21.c1229 if (!mode_lib->vba.IgnoreViewportPositioning) { in CalculatePrefetchSourceLines()
1336 …MPDEBytesFrame = 128 * ((mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPage… in CalculateVMAndRowBytes()
1366 …if (GPUVMEnable == true && (mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxP… in CalculateVMAndRowBytes()
1372 …ExtraDPDEBytesFrame = 128 * ((mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMa… in CalculateVMAndRowBytes()
1471 struct vba_vars_st *locals = &mode_lib->vba; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1474 mode_lib->vba.WritebackDISPCLK = 0.0; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1475 mode_lib->vba.DISPCLKWithRamping = 0; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1476 mode_lib->vba.DISPCLKWithoutRamping = 0; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1477 mode_lib->vba.GlobalDPPCLK = 0.0; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1481 for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddcn30_fpu.c362 …wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[cur_… in dcn30_fpu_set_mcif_arb_params()
385 int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; in dcn30_fpu_calculate_wm_and_dlg()
387 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
388 …bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clo… in dcn30_fpu_calculate_wm_and_dlg()
419 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; in dcn30_fpu_calculate_wm_and_dlg()
420 dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
421 …pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_ch… in dcn30_fpu_calculate_wm_and_dlg()
484 unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; in dcn30_fpu_calculate_wm_and_dlg()
490 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] == in dcn30_fpu_calculate_wm_and_dlg()
548 context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod; in dcn30_fpu_calculate_wm_and_dlg()
[all …]
Ddisplay_mode_vba_30.c1628 if (!mode_lib->vba.IgnoreViewportPositioning) { in CalculatePrefetchSourceLines()
1732 MPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 1); in CalculateVMAndRowBytes()
1753 if (GPUVMEnable == true && mode_lib->vba.GPUVMMaxPageTableLevels > 1) { in CalculateVMAndRowBytes()
1759 ExtraDPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 2); in CalculateVMAndRowBytes()
1855 struct vba_vars_st *v = &mode_lib->vba; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3072 for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { in DisplayPipeConfiguration()
3075 mode_lib->vba.SourcePixelFormat[k], in DisplayPipeConfiguration()
3076 mode_lib->vba.SurfaceTiling[k], in DisplayPipeConfiguration()
3088 mode_lib->vba.NumberOfActivePlanes, in DisplayPipeConfiguration()
3089 mode_lib->vba.DETBufferSizeInKByte[0], in DisplayPipeConfiguration()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/
Ddml2_mall_phantom.c235 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in assign_subvp_pipe() local
257 …vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plan… in assign_subvp_pipe()
604 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dml2_svp_validate_static_schedulability() local
623 if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 && in dml2_svp_validate_static_schedulability()
Ddml2_wrapper.c657 context->bw_ctx.dml.vba.StutterPeriod = context->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriod; in dml2_validate_and_build_resource()
661 if (context->bw_ctx.dml.vba.StutterPeriod < in_dc->debug.minimum_z8_residency_time && in dml2_validate_and_build_resource()
/linux-6.12.1/mm/
Dpagewalk.c622 pgoff_t vba, vea, cba, cea; in walk_page_mapping() local
630 vba = vma->vm_pgoff; in walk_page_mapping()
631 vea = vba + vma_pages(vma); in walk_page_mapping()
633 cba = max(cba, vba); in walk_page_mapping()
637 start_addr = ((cba - vba) << PAGE_SHIFT) + vma->vm_start; in walk_page_mapping()
638 end_addr = ((cea - vba) << PAGE_SHIFT) + vma->vm_start; in walk_page_mapping()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddcn31_fpu.c471 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->… in dcn315_update_soc_for_wm_a()
489 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
562 …context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_d… in dcn31_calculate_wm_and_dlg_fp()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn30/
Ddcn30_resource.c1640 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn30_internal_validate_bw() local
1646 context->bw_ctx.dml.vba.maxMpcComb = 0; in dcn30_internal_validate_bw()
1647 context->bw_ctx.dml.vba.VoltageLevel = 0; in dcn30_internal_validate_bw()
1648 context->bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive; in dcn30_internal_validate_bw()
1674 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) { in dcn30_internal_validate_bw()
1709 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn30_internal_validate_bw()
1778 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled; in dcn30_internal_validate_bw()
1864 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; in dcn30_internal_validate_bw()
1870 context->bw_ctx.dml.vba.VoltageLevel = vlevel; in dcn30_internal_validate_bw()
2087 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dcn30_validate_bandwidth()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn21/
Ddcn21_resource.c825 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn21_fast_validate_bw() local
831 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn21_fast_validate_bw()
855 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
879 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn21_fast_validate_bw()
883 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
905 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn21_fast_validate_bw()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn35/
Ddcn35_fpu.c566 context->bw_ctx.dml.vba.ODMCombinePolicy = in dcn35_populate_dml_pipes_from_context_fpu()
597 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in dcn35_decide_zstate_support()
600 bool allow_z10 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z10_residency; in dcn35_decide_zstate_support()
613 (int)context->bw_ctx.dml.vba.StutterPeriod); in dcn35_decide_zstate_support()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/core/
Ddc_hw_sequencer.c505 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in set_p_state_switch_method() local
508 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba) in set_p_state_switch_method()
511 if (vba->DRAMClockChangeSupport[vba->VoltageLevel][vba->maxMpcComb] != in set_p_state_switch_method()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/
Ddcn32_resource_helpers.c711 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn32_subvp_vblank_admissable() local
744 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) in dcn32_subvp_vblank_admissable()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn20/
Ddcn20_resource.c1855 struct vba_vars_st *v = &context->bw_ctx.dml.vba; in dcn20_validate_apply_pipe_split_flags()
2083 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2102 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) in dcn20_fast_validate_bw()
2112 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn20_fast_validate_bw()
2116 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2138 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
/linux-6.12.1/drivers/parisc/
Dccio-dma.c546 ccio_io_pdir_entry(__le64 *pdir_ptr, space_t sid, unsigned long vba, in ccio_io_pdir_entry() argument
560 pa = lpa(vba); in ccio_io_pdir_entry()
585 asm volatile ("lci %%r0(%1), %0" : "=r" (ci) : "r" (vba)); in ccio_io_pdir_entry()
Dsba_iommu.c572 sba_io_pdir_entry(__le64 *pdir_ptr, space_t sid, unsigned long vba, in sba_io_pdir_entry() argument
578 pa = lpa(vba); in sba_io_pdir_entry()
581 asm("lci 0(%1), %0" : "=r" (ci) : "r" (vba)); in sba_io_pdir_entry()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn351/
Ddcn351_fpu.c600 context->bw_ctx.dml.vba.ODMCombinePolicy = in dcn351_populate_dml_pipes_from_context_fpu()
631 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in dcn351_decide_zstate_support()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn314/
Ddcn314_fpu.c422 context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; in dcn314_populate_dml_pipes_from_context_fpu()

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