Searched refs:ubwc_swizzle (Results 1 – 7 of 7) sorted by relevance
182 u32 value = (data->ubwc_swizzle & 0x1) | in msm_mdss_setup_ubwc_dec_30()198 u32 value = (data->ubwc_swizzle & 0x7) | in msm_mdss_setup_ubwc_dec_40()587 .ubwc_swizzle = 6,605 .ubwc_swizzle = 6,629 .ubwc_swizzle = 6,652 .ubwc_swizzle = 7,661 .ubwc_swizzle = 1,668 .ubwc_swizzle = 6,679 .ubwc_swizzle = 6,690 .ubwc_swizzle = 6,[all …]
13 u32 ubwc_swizzle; member
283 fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) | in dpu_hw_sspp_setup_format()290 fast_clear | (ctx->ubwc->ubwc_swizzle) | in dpu_hw_sspp_setup_format()295 BIT(30) | (ctx->ubwc->ubwc_swizzle) | in dpu_hw_sspp_setup_format()
509 gpu->ubwc_config.ubwc_swizzle = 0x6; in a6xx_calc_ubwc_config()516 gpu->ubwc_config.ubwc_swizzle = 0x7; in a6xx_calc_ubwc_config()580 u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1; in a6xx_set_ubwc_config()581 u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2); in a6xx_set_ubwc_config()
213 u32 ubwc_swizzle; member
383 *value = adreno_gpu->ubwc_config.ubwc_swizzle; in adreno_get_param()
1806 adreno_gpu->ubwc_config.ubwc_swizzle = 0x7; in a5xx_gpu_init()