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Searched refs:tx_reg (Results 1 – 17 of 17) sorted by relevance

/linux-6.12.1/drivers/mailbox/
Darm_mhu.c30 void __iomem *tx_reg; member
61 u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS); in mhu_last_tx_done()
71 writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS); in mhu_send_data()
82 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS); in mhu_startup()
83 writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS); in mhu_startup()
133 mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET; in mhu_probe()
Dplatform_mhu.c36 void __iomem *tx_reg; member
67 u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS); in platform_mhu_last_tx_done()
77 writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS); in platform_mhu_send_data()
88 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS); in platform_mhu_startup()
89 writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS); in platform_mhu_startup()
142 mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET; in platform_mhu_probe()
Darm_mhu_db.c34 void __iomem *tx_reg; member
140 void __iomem *base = chan_info->mhu->mlink[chan_info->pchan].tx_reg; in mhu_db_last_tx_done()
151 void __iomem *base = chan_info->mhu->mlink[chan_info->pchan].tx_reg; in mhu_db_send_data()
315 mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET; in mhu_db_probe()
/linux-6.12.1/drivers/net/wireless/ath/ath5k/
Ddma.c355 u16 tx_reg; in ath5k_hw_get_txdp() local
366 tx_reg = AR5K_NOQCU_TXDP0; in ath5k_hw_get_txdp()
370 tx_reg = AR5K_NOQCU_TXDP1; in ath5k_hw_get_txdp()
376 tx_reg = AR5K_QUEUE_TXDP(queue); in ath5k_hw_get_txdp()
379 return ath5k_hw_reg_read(ah, tx_reg); in ath5k_hw_get_txdp()
398 u16 tx_reg; in ath5k_hw_set_txdp() local
409 tx_reg = AR5K_NOQCU_TXDP0; in ath5k_hw_set_txdp()
413 tx_reg = AR5K_NOQCU_TXDP1; in ath5k_hw_set_txdp()
427 tx_reg = AR5K_QUEUE_TXDP(queue); in ath5k_hw_set_txdp()
431 ath5k_hw_reg_write(ah, phys_addr, tx_reg); in ath5k_hw_set_txdp()
/linux-6.12.1/drivers/spi/
Dspi-orion.c385 void __iomem *tx_reg, *rx_reg, *int_reg; in orion_spi_write_read_8bit() local
396 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); in orion_spi_write_read_8bit()
404 writel(*(*tx_buf)++, tx_reg); in orion_spi_write_read_8bit()
406 writel(0, tx_reg); in orion_spi_write_read_8bit()
434 void __iomem *tx_reg, *rx_reg, *int_reg; in orion_spi_write_read_16bit() local
443 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); in orion_spi_write_read_16bit()
451 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg); in orion_spi_write_read_16bit()
453 writel(0, tx_reg); in orion_spi_write_read_16bit()
Dspi-omap2-mcspi.c708 void __iomem *tx_reg; in omap2_mcspi_txrx_pio() local
721 tx_reg = base + OMAP2_MCSPI_TX0; in omap2_mcspi_txrx_pio()
745 writel_relaxed(*tx++, tx_reg); in omap2_mcspi_txrx_pio()
794 writel_relaxed(*tx++, tx_reg); in omap2_mcspi_txrx_pio()
843 writel_relaxed(*tx++, tx_reg); in omap2_mcspi_txrx_pio()
Dspi-topcliff-pch.c845 param->tx_reg = data->io_base_addr + PCH_SPDWR; in pch_spi_request_dma()
/linux-6.12.1/include/linux/
Dpch_dma.h20 dma_addr_t tx_reg; member
/linux-6.12.1/arch/mips/include/asm/txx9/
Ddmac.h40 u64 tx_reg; member
/linux-6.12.1/drivers/dma/
Dtxx9dmac.c351 if (ds->tx_reg) { in txx9dmac_dostart()
372 if (ds->tx_reg) { in txx9dmac_dostart()
818 if (ds->tx_reg) in txx9dmac_prep_slave_sg()
843 desc->hwdesc.DAR = ds->tx_reg; in txx9dmac_prep_slave_sg()
852 desc->hwdesc32.DAR = ds->tx_reg; in txx9dmac_prep_slave_sg()
1011 (ds->tx_reg && ds->rx_reg) || (!ds->tx_reg && !ds->rx_reg)) in txx9dmac_alloc_chan_resources()
Dpch_dma.c583 reg = pd_slave->tx_reg; in pd_prep_slave_sg()
/linux-6.12.1/drivers/media/rc/
Dene_ir.h209 int tx_reg; /* current reg used for TX */ member
Dene_ir.c650 dev->tx_reg ? ENE_CIRRLC_OUT1 : ENE_CIRRLC_OUT0, raw_tx); in ene_tx_sample()
652 dev->tx_reg = !dev->tx_reg; in ene_tx_sample()
961 dev->tx_reg = 0; in ene_transmit()
/linux-6.12.1/drivers/slimbus/
Dqcom-ctrl.c121 u8 len, u32 tx_reg) in qcom_slim_queue_tx() argument
125 __iowrite32_copy(ctrl->base + tx_reg, buf, count); in qcom_slim_queue_tx()
/linux-6.12.1/drivers/net/phy/
Dmotorcomm.c872 u32 rx_reg, tx_reg; in ytphy_rgmii_clk_delay_config() local
880 tx_reg = ytphy_get_delay_reg_value(phydev, "tx-internal-delay-ps", in ytphy_rgmii_clk_delay_config()
893 val |= FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); in ytphy_rgmii_clk_delay_config()
897 FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); in ytphy_rgmii_clk_delay_config()
/linux-6.12.1/drivers/net/ethernet/intel/i40e/
Di40e_main.c4689 u32 tx_reg; in i40e_pf_txq_wait() local
4692 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q)); in i40e_pf_txq_wait()
4693 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) in i40e_pf_txq_wait()
4717 u32 tx_reg; in i40e_control_tx_q() local
4726 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q)); in i40e_control_tx_q()
4727 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) == in i40e_control_tx_q()
4728 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1)) in i40e_control_tx_q()
4734 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) in i40e_control_tx_q()
4740 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK; in i40e_control_tx_q()
4742 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; in i40e_control_tx_q()
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/linux-6.12.1/drivers/tty/serial/
Dpch_uart.c687 param->tx_reg = port->mapbase + UART_TX; in pch_request_dma()