| /linux-6.12.1/arch/arm64/include/asm/ |
| D | mmu_context.h | 44 unsigned long ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); in cpu_set_reserved_ttbr0_nosync() local
46 write_sysreg(ttbr, ttbr0_el1); in cpu_set_reserved_ttbr0_nosync()
212 u64 ttbr; in update_saved_ttbr0() local
218 ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); in update_saved_ttbr0()
220 ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48; in update_saved_ttbr0()
222 WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); in update_saved_ttbr0()
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| D | assembler.h | 586 .macro offset_ttbr1, ttbr, tmp
591 orr \tmp, \ttbr, #TTBR1_BADDR_4852_OFFSET
592 csel \ttbr, \tmp, \ttbr, eq
603 .macro phys_to_ttbr, ttbr, phys
605 orr \ttbr, \phys, \phys, lsr #46
606 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
608 mov \ttbr, \phys
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| D | uaccess.h | 61 unsigned long flags, ttbr; in __uaccess_ttbr0_disable() local
64 ttbr = read_sysreg(ttbr1_el1); in __uaccess_ttbr0_disable()
65 ttbr &= ~TTBR_ASID_MASK; in __uaccess_ttbr0_disable()
67 write_sysreg(ttbr - RESERVED_SWAPPER_OFFSET, ttbr0_el1); in __uaccess_ttbr0_disable()
69 write_sysreg(ttbr, ttbr1_el1); in __uaccess_ttbr0_disable()
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| /linux-6.12.1/drivers/gpu/drm/msm/ |
| D | msm_iommu.c | 27 phys_addr_t ttbr; member
173 phys_addr_t *ttbr, int *asid) in msm_iommu_pagetable_params() argument
182 if (ttbr) in msm_iommu_pagetable_params()
183 *ttbr = pagetable->ttbr; in msm_iommu_pagetable_params()
309 pagetable->ttbr = ttbr0_cfg.arm_lpae_s1_cfg.ttbr; in msm_iommu_pagetable_create()
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| D | msm_mmu.h | 55 int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr,
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| /linux-6.12.1/arch/arm/include/asm/ |
| D | proc-fns.h | 158 u64 ttbr; \
160 : "=r" (ttbr)); \
161 ttbr; \
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| /linux-6.12.1/include/linux/ |
| D | io-pgtable.h | 133 u64 ttbr; member
159 u32 ttbr; member
171 u64 ttbr[4]; member
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| /linux-6.12.1/drivers/iommu/arm/arm-smmu/ |
| D | arm-smmu-qcom.c | 158 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); in qcom_adreno_smmu_set_ttbr0_cfg()
170 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in qcom_adreno_smmu_set_ttbr0_cfg()
171 cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); in qcom_adreno_smmu_set_ttbr0_cfg()
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| D | arm-smmu.c | 537 cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr; in arm_smmu_init_context_bank()
538 cb->ttbr[1] = 0; in arm_smmu_init_context_bank()
540 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
542 cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
546 cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
548 cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
551 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; in arm_smmu_init_context_bank()
626 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
627 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR1, cb->ttbr[1]); in arm_smmu_write_context_bank()
629 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
[all …]
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| D | arm-smmu.h | 364 u64 ttbr[2]; member
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| D | qcom_iommu.c | 281 pgtbl_cfg.arm_lpae_s1_cfg.ttbr | in qcom_iommu_init_domain()
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| /linux-6.12.1/arch/arm64/kernel/pi/ |
| D | map_kernel.c | 135 static void noinline __section(".idmap.text") set_ttbr0_for_lpa2(u64 ttbr) in set_ttbr0_for_lpa2() argument
150 :: "r"(sctlr & ~SCTLR_ELx_M), "r"(ttbr), "r"(tcr), "r"(sctlr)); in set_ttbr0_for_lpa2()
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| /linux-6.12.1/drivers/iommu/ |
| D | apple-dart.c | 147 #define DART_TTBR(dart, sid, idx) ((dart)->hw->ttbr + \
181 u64 ttbr; member
565 pgtbl_cfg->apple_dart_cfg.ttbr[i]); in apple_dart_setup_translation()
1215 .ttbr = DART_T8020_TTBR,
1241 .ttbr = DART_T8020_USB4_TTBR,
1267 .ttbr = DART_T8020_TTBR,
1292 .ttbr = DART_T8110_TTBR,
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| D | ipmmu-vmsa.c | 366 u64 ttbr; in ipmmu_domain_setup_context() local
370 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr; in ipmmu_domain_setup_context()
371 ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); in ipmmu_domain_setup_context()
372 ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); in ipmmu_domain_setup_context()
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| D | io-pgtable-dart.c | 419 cfg->apple_dart_cfg.ttbr[i] = virt_to_phys(data->pgd[i]); in apple_dart_alloc_pgtable()
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| D | io-pgtable-arm-v7s.c | 872 cfg->arm_v7s_cfg.ttbr = paddr | upper_32_bits(paddr); in arm_v7s_alloc_pgtable()
874 cfg->arm_v7s_cfg.ttbr = paddr | ARM_V7S_TTBR_S | in arm_v7s_alloc_pgtable()
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| D | mtk_iommu.c | 755 writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_attach_device()
1496 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_runtime_resume()
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| D | msm_iommu.c | 274 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr); in __program_context()
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| D | io-pgtable-arm.c | 1023 cfg->arm_lpae_s1_cfg.ttbr = virt_to_phys(data->pgd); in arm_64_lpae_alloc_pgtable_s1()
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| /linux-6.12.1/arch/arm64/kvm/ |
| D | at.c | 93 u64 hcr, sctlr, tcr, tg, ps, ia_bits, ttbr; in setup_s1_walk() local
113 ttbr = (va55 ? in setup_s1_walk()
121 ttbr = (va55 ? in setup_s1_walk()
269 wi->baddr = ttbr & TTBRx_EL1_BADDR; in setup_s1_walk()
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| /linux-6.12.1/drivers/gpu/drm/msm/adreno/ |
| D | a6xx_gpu.c | 109 phys_addr_t ttbr; in a6xx_set_pagetable() local
116 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) in a6xx_set_pagetable()
141 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); in a6xx_set_pagetable()
144 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | in a6xx_set_pagetable()
155 OUT_RING(ring, lower_32_bits(ttbr)); in a6xx_set_pagetable()
156 OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr)); in a6xx_set_pagetable()
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| /linux-6.12.1/drivers/iommu/arm/arm-smmu-v3/ |
| D | arm-smmu-v3-test.c | 465 io_pgtable.cfg.arm_lpae_s1_cfg.ttbr = 0xdaedbeefdeadbeefULL; in arm_smmu_test_make_s1_cd()
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| D | arm-smmu-v3.c | 1388 target->data[1] = cpu_to_le64(pgtbl_cfg->arm_lpae_s1_cfg.ttbr & in arm_smmu_make_s1_cd()
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| /linux-6.12.1/drivers/gpu/drm/panthor/ |
| D | panthor_mmu.c | 766 transtab = cfg->arm_lpae_s1_cfg.ttbr; in panthor_vm_active()
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