Searched refs:tile0 (Results 1 – 3 of 3) sorted by relevance
/linux-6.12.1/drivers/gpu/drm/xe/display/ |
D | xe_plane_initial.c | 60 struct xe_tile *tile0 = xe_device_get_root_tile(xe); in initial_plane_bo() local 73 u64 __iomem *gte = tile0->mem.ggtt->gsm; in initial_plane_bo() 92 if (phys_base >= tile0->mem.vram.usable_size) { in initial_plane_bo() 127 bo = xe_bo_create_pin_map_at(xe, tile0, NULL, size, phys_base, in initial_plane_bo()
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D | xe_fb_pin.c | 85 struct xe_tile *tile0 = xe_device_get_root_tile(xe); in __xe_pin_fb_vma_dpt() local 86 struct xe_ggtt *ggtt = tile0->mem.ggtt; in __xe_pin_fb_vma_dpt() 101 dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size, in __xe_pin_fb_vma_dpt() 107 dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size, in __xe_pin_fb_vma_dpt() 113 dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size, in __xe_pin_fb_vma_dpt()
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/linux-6.12.1/drivers/media/platform/verisilicon/ |
D | rockchip_vpu981_hw_av1_dec.c | 582 int tile0, tile1; in rockchip_vpu981_av1_dec_set_tile_info() local 586 for (tile0 = 0; tile0 < tile_info->tile_cols; tile0++) { in rockchip_vpu981_av1_dec_set_tile_info() 588 int tile_id = tile1 * tile_info->tile_cols + tile0; in rockchip_vpu981_av1_dec_set_tile_info() 592 u32 x0 = tile_info->width_in_sbs_minus_1[tile0] + 1; in rockchip_vpu981_av1_dec_set_tile_info()
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