| /linux-6.12.1/arch/mips/boot/compressed/ |
| D | head.S | 35 PTR_LA t9, decompress_kernel
36 jalr t9
43 PTR_LI t9, KERNEL_ENTRY
44 jalr t9
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| /linux-6.12.1/arch/mips/loongson64/ |
| D | sleeper.S | 14 move t9, a0
17 jalr t9
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| /linux-6.12.1/arch/mips/kernel/ |
| D | octeon_switch.S | 48 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
53 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
65 LONG_L t9, TASK_STACK_CANARY(a1)
66 LONG_S t9, 0(t8)
99 dmfc0 t9, $9,7 /* CvmCtl register. */
108 bbit1 t9, 28, 1f
116 1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
262 dmfc0 t9, $9,7 /* CvmCtl register. */
273 bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
283 bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */
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| D | cps-vec.S | 143 move a1, t9
282 li t9, 0
291 mfc0 t9, CP0_GLOBALNUMBER
292 andi t9, t9, MIPS_GLOBALNUMBER_VP
311 mfc0 t9, $15, 1
312 and t9, t9, t1
317 mul v1, t9, t1
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| D | r2300_switch.S | 40 LONG_L t9, TASK_STACK_CANARY(a1)
41 LONG_S t9, 0(t8)
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| D | r4k_switch.S | 36 LONG_L t9, TASK_STACK_CANARY(a1)
37 LONG_S t9, 0(t8)
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| D | cps-vec-ns16550.S | 37 1: UART_L t0, UART_LSR_OFS(t9)
40 UART_S a0, UART_TX_OFS(t9)
176 li t9, CKSEG1ADDR(CONFIG_MIPS_CPS_NS16550_BASE)
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| /linux-6.12.1/arch/mips/include/asm/mach-loongson64/ |
| D | kernel-entry-init.h | 93 2: li t9, 0x100 /* wait for init loop */
94 3: addiu t9, -1 /* limit mailbox access */
95 bnez t9, 3b
|
| /linux-6.12.1/arch/alpha/lib/ |
| D | stxcpy.S | 39 .frame sp, 0, t9
91 ret (t9) # .. e1 :
99 .frame sp, 0, t9
230 ret (t9) # .. e1 :
288 ret (t9) # e1 :
|
| D | ev6-stxcpy.S | 50 .frame sp, 0, t9
109 ret (t9) # L0 : Latency=3
119 .frame sp, 0, t9
259 ret (t9) # L0 : Latency=3
318 ret (t9) # e1 :
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| D | stxncpy.S | 47 .frame sp, 0, t9, 0
105 ret (t9) # e1 :
118 .frame sp, 0, t9, 0
266 ret (t9) # .. e1 :
344 ret (t9) # .. e1 :
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| D | ev6-stxncpy.S | 58 .frame sp, 0, t9, 0
133 ret (t9) # L0 : Latency=3
150 .frame sp, 0, t9, 0
312 ret (t9) # L0 : Latency=3
393 ret (t9) # L0 : Latency=3
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| /linux-6.12.1/arch/mips/include/asm/ |
| D | regdef.h | 141 #define t9 $25
184 #define t9 $25 /* callee address for PIC/temp */
|
| /linux-6.12.1/tools/perf/util/hisi-ptt-decoder/ |
| D | hisi-ptt-pkt-decoder.c | 80 uint32_t t9 : 1; member
138 "Format", dw0.format, "Type", dw0.type, "T9", dw0.t9, in hisi_ptt_4dw_print_dw0()
|
| /linux-6.12.1/arch/alpha/include/uapi/asm/ |
| D | regdef.h | 33 #define t9 $23 macro
|
| /linux-6.12.1/arch/arm64/crypto/ |
| D | ghash-ce-core.S | 31 t9 .req v16
106 pmull\t t9.8h, \ad, \b4\().\nb // K = A*B4
115 uzp1 t6.2d, t7.2d, t9.2d
116 uzp2 t7.2d, t7.2d, t9.2d
133 zip2 t9.2d, t6.2d, t7.2d
139 ext t9.16b, t9.16b, t9.16b, #12
142 eor t7.16b, t7.16b, t9.16b
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| D | crct10dif-ce-core.S | 89 t9 .req v23
145 pmull t9.8h, ad.8b, bd3.8b // I = A*B3
159 pmull2 t9.8h, ad.16b, bd3.16b // I = A*B3
164 eor t6.16b, t6.16b, t9.16b // N = I + J
|
| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_pps.c | 1329 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1352 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); in intel_pps_dump_state()
1364 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || in intel_pps_verify_state()
1374 return delays->t1_t3 || delays->t8 || delays->t9 || in pps_delays_valid()
1436 spec->t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ in pps_init_delays_spec()
1470 assign_final(t9); in pps_init_delays()
1478 intel_dp->pps.backlight_off_delay = get_delay(t9); in pps_init_delays()
1501 final->t9 = 1; in pps_init_delays()
1553 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | in pps_init_registers()
|
| D | intel_bios.h | 56 u16 t9; member
|
| /linux-6.12.1/arch/mips/lib/ |
| D | memset.S | 103 move t9, a1
|
| /linux-6.12.1/tools/testing/selftests/bpf/prog_tests/ |
| D | btf_dump.c | 419 long double t9 = 0.0; in test_btf_dump_float_data() local
448 ASSERT_OK(btf_dump_data(btf, d, "test_long_double", NULL, 0, &t9, 16, in test_btf_dump_float_data()
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| /linux-6.12.1/drivers/gpu/drm/gma500/ |
| D | intel_bios.h | 447 u16 t9; member
|
| D | cdv_intel_dp.c | 2039 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> in cdv_intel_dp_init()
2049 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); in cdv_intel_dp_init()
2054 intel_dp->backlight_off_delay = cur.t9 / 10; in cdv_intel_dp_init()
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| D | intel_bios.c | 85 dev_priv->edp.pps.t9, dev_priv->edp.pps.t10, in parse_edp()
|
| /linux-6.12.1/arch/mips/crypto/ |
| D | chacha-core.S | 20 #define X9 $t9
|