Searched refs:sync_offset (Results 1 – 15 of 15) sorted by relevance
| /linux-6.12.1/drivers/gpu/host1x/ |
| D | dev.c | 62 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; in host1x_sync_writel()
69 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; in host1x_sync_readl()
90 .sync_offset = 0x3000,
105 .sync_offset = 0x3000,
120 .sync_offset = 0x2100,
135 .sync_offset = 0x2100,
165 .sync_offset = 0x0,
202 .sync_offset = 0x0,
274 .sync_offset = 0x0,
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| D | dev.h | 105 unsigned int sync_offset; /* offset of syncpoint registers */ member
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| /linux-6.12.1/drivers/scsi/ |
| D | dc395x.c | 274 u8 sync_offset; /* for reg. and nego.(low nibble) */ member
1130 dcb->sync_offset = 0; in reset_dev_param()
1263 dcb->sync_offset = 0; in build_sdtr()
1265 } else if (dcb->sync_offset == 0) in build_sdtr()
1266 dcb->sync_offset = SYNC_NEGO_OFFSET; in build_sdtr()
1269 dcb->sync_offset); in build_sdtr()
1388 DC395x_write8(acb, TRM_S1040_SCSI_OFFSET, dcb->sync_offset); in start_scsi()
2531 DC395x_write8(acb, TRM_S1040_SCSI_OFFSET, dcb->sync_offset); in reprogram_regs()
2546 dcb->sync_offset = 0; in msgin_set_async()
2575 dcb->sync_offset = 0; in msgin_set_sync()
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| D | mac53c94.h | 56 #define sync_offset flags macro
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| D | wd719x.h | 54 u8 sync_offset; /* 60 Synchronous offset */ member
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| D | mac53c94.c | 135 writeb(0, ®s->sync_offset); in mac53c94_init()
167 writeb(0, ®s->sync_offset); in mac53c94_start()
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| D | qla1280.h | 464 uint8_t sync_offset:4; member
471 uint8_t sync_offset:5; member
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| D | qla1280.c | 1132 mb[3] = (nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8); in qla1280_set_target_parameters()
1137 mb[3] = (nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8); in qla1280_set_target_parameters()
1995 nv->bus[bus].target[target].flags.flags1x160.sync_offset = 0x0e; in qla1280_set_target_defaults()
2002 nv->bus[bus].target[target].flags.flags1x80.sync_offset = 12; in qla1280_set_target_defaults()
2082 mb[3] = nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8; in qla1280_config_target()
2084 mb[3] = nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8; in qla1280_config_target()
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| D | myrb.h | 410 unsigned int sync_offset:5; /* Byte 5 Bits 0-4 */ member
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| D | BusLogic.h | 1050 unsigned char sync_offset[BLOGIC_MAXDEV]; member
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| D | BusLogic.c | 2101 …adapter->sync_offset[tgt_id] = (tgt_id < 8 ? setupinfo.sync0to7[tgt_id].offset : setupinfo.sync8to… in blogic_inquiry()
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| /linux-6.12.1/sound/firewire/dice/ |
| D | dice-transaction.c | 22 offset += dice->sync_offset; in get_subaddr()
334 dice->sync_offset = be32_to_cpu(pointers[6]) * 4; in get_subaddrs()
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| D | dice.h | 85 unsigned int sync_offset; member
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| /linux-6.12.1/drivers/scsi/sym53c8xx_2/ |
| D | sym_nvram.h | 94 u_char sync_offset; member
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| /linux-6.12.1/drivers/net/ethernet/broadcom/bnx2x/ |
| D | bnx2x_link.c | 4809 u32 sync_offset, media_types; in bnx2x_link_status_update() local
4830 sync_offset = params->shmem_base + in bnx2x_link_status_update()
4833 media_types = REG_RD(bp, sync_offset); in bnx2x_link_status_update()
4847 sync_offset = params->shmem_base + in bnx2x_link_status_update()
4851 vars->aeu_int_mask = REG_RD(bp, sync_offset); in bnx2x_link_status_update()
8124 u32 sync_offset = 0, phy_idx, media_types; in bnx2x_get_edc_mode() local
8222 sync_offset = params->shmem_base + in bnx2x_get_edc_mode()
8225 media_types = REG_RD(bp, sync_offset); in bnx2x_get_edc_mode()
8237 REG_WR(bp, sync_offset, media_types); in bnx2x_get_edc_mode()
12591 u32 phy_config_swapped, sync_offset, media_types; in bnx2x_phy_probe() local
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