| /linux-6.12.1/arch/arm/include/asm/mach/ |
| D | pci.h | 27 u8 (*swizzle)(struct pci_dev *dev, u8 *pin); member
44 u8 (*swizzle)(struct pci_dev *, u8 *); member
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| /linux-6.12.1/drivers/gpu/drm/i915/gem/selftests/ |
| D | i915_gem_client_blt.c | 34 int swizzle, subtile; in linear_x_y_to_ftiled_pos() local
70 swizzle = f_subtile_map[subtile]; in linear_x_y_to_ftiled_pos()
74 swizzle * F_SUBTILE_SIZE + in linear_x_y_to_ftiled_pos()
353 unsigned int swizzle; in tiled_offset() local
367 swizzle = gt->ggtt->bit_6_swizzle_x; in tiled_offset()
373 swizzle = I915_BIT_6_SWIZZLE_NONE; in tiled_offset()
383 swizzle = gt->ggtt->bit_6_swizzle_y; in tiled_offset()
386 switch (swizzle) { in tiled_offset()
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| D | i915_gem_mman.c | 36 unsigned int swizzle; member
74 switch (tile->swizzle) { in tiled_offset()
358 tile.swizzle = I915_BIT_6_SWIZZLE_NONE; in igt_partial_tiling()
383 tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_x; in igt_partial_tiling()
386 tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_y; in igt_partial_tiling()
390 GEM_BUG_ON(tile.swizzle == I915_BIT_6_SWIZZLE_UNKNOWN); in igt_partial_tiling()
391 if (tile.swizzle == I915_BIT_6_SWIZZLE_9_17 || in igt_partial_tiling()
392 tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17) in igt_partial_tiling()
499 tile.swizzle = I915_BIT_6_SWIZZLE_NONE; in igt_smoke_tiling()
503 tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_x; in igt_smoke_tiling()
[all …]
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| /linux-6.12.1/arch/arm/kernel/ |
| D | bios32.c | 365 if (sys->swizzle) in pcibios_swizzle()
366 slot = sys->swizzle(dev, pin); in pcibios_swizzle()
443 sys->swizzle = hw->swizzle; in pcibios_init_hw()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | dchubbub.h | 158 enum swizzle_mode_values swizzle,
164 enum swizzle_mode_addr3_values swizzle,
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_display.c | 763 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); in convert_tiling_flags_to_modifier() local
764 bool has_xor = swizzle >= 16; in convert_tiling_flags_to_modifier()
774 switch (swizzle >> 2) { in convert_tiling_flags_to_modifier()
806 switch (swizzle & 3) { in convert_tiling_flags_to_modifier()
1074 int swizzle = AMD_FMT_MOD_GET(TILE, modifier); in amdgpu_display_verify_sizes() local
1076 switch (swizzle) { in amdgpu_display_verify_sizes()
1091 "Gfx12 swizzle mode with unknown block size: %d\n", swizzle); in amdgpu_display_verify_sizes()
1098 int swizzle = AMD_FMT_MOD_GET(TILE, modifier); in amdgpu_display_verify_sizes() local
1100 switch ((swizzle & ~3) + 1) { in amdgpu_display_verify_sizes()
1118 "Swizzle mode with unknown block size: %d\n", swizzle); in amdgpu_display_verify_sizes()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_debug.c | 172 plane_state->tiling_info.gfx9.swizzle); in pre_surface_trace()
258 update->plane_info->tiling_info.gfx9.swizzle); in update_surface_trace()
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| /linux-6.12.1/drivers/gpu/drm/ci/xfails/ |
| D | amdgpu-stoney-fails.txt | 15 amdgpu/amd_plane@mpo-swizzle-toggle,Fail
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/ |
| D | dcn30_hubbub.c | 138 enum swizzle_mode_values swizzle, in hubbub3_dcc_support_swizzle() argument
147 switch (swizzle) { in hubbub3_dcc_support_swizzle()
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| D | dcn30_hubbub.h | 114 enum swizzle_mode_values swizzle,
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/ |
| D | dcn20_hubbub.h | 108 enum swizzle_mode_values swizzle,
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| D | dcn20_hubbub.c | 57 enum swizzle_mode_values swizzle, in hubbub2_dcc_support_swizzle() argument
66 switch (swizzle) { in hubbub2_dcc_support_swizzle()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_trace.h | 418 __field(int, swizzle)
450 __entry->swizzle = plane_state->tiling_info.gfx9.swizzle;
484 __entry->swizzle,
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| D | amdgpu_dm_plane.c | 285 input.swizzle_mode = tiling_info->gfx9.swizzle; in amdgpu_dm_plane_validate_dcc()
319 tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier); in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
372 tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier); in amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| D | dcn10_resource.c | 1228 enum swizzle_mode_values swizzle = DC_SW_LINEAR; in dcn10_patch_unknown_plane_state() local
1231 swizzle = DC_SW_64KB_D; in dcn10_patch_unknown_plane_state()
1233 swizzle = DC_SW_64KB_S; in dcn10_patch_unknown_plane_state()
1235 plane_state->tiling_info.gfx9.swizzle = swizzle; in dcn10_patch_unknown_plane_state()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/ |
| D | dc_hw_types.h | 409 enum swizzle_mode_values swizzle; member
425 enum swizzle_mode_addr3_values swizzle; member
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| /linux-6.12.1/drivers/gpu/drm/i915/ |
| D | i915_debugfs.c | 304 static const char *swizzle_string(unsigned swizzle) in swizzle_string() argument
306 switch (swizzle) { in swizzle_string()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/ |
| D | dcn401_hubbub.h | 154 enum swizzle_mode_addr3_values swizzle,
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| D | dcn401_hubbub.c | 602 enum swizzle_mode_addr3_values swizzle, in hubbub401_dcc_support_swizzle() argument
610 switch (swizzle) { in hubbub401_dcc_support_swizzle()
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| /linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/ |
| D | com.fuc | 416 // Calculates the hw swizzle mask and adjusts the surface's xcnt to match
419 // zero out a chunk of the stack to store the swizzle into
435 // convert FORMAT swizzle mask to hw swizzle mask
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/ |
| D | dcn10_hubbub.c | 711 enum swizzle_mode_values swizzle, in hubbub1_dcc_support_swizzle() argument
719 switch (swizzle) { in hubbub1_dcc_support_swizzle()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn30/ |
| D | dcn30_hubp.c | 331 SW_MODE, info->gfx9.swizzle, in hubp3_program_tiling()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| D | dcn_calcs.c | 339 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; in pipe_ctx_to_e2e_pipe_params()
348 …src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle); in pipe_ctx_to_e2e_pipe_params()
1010 pipe->plane_state->tiling_info.gfx9.swizzle); in dcn_validate_bandwidth()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.c | 1254 enum swizzle_mode_values swizzle, in swizzle_to_dml_params() argument
1257 switch (swizzle) { in swizzle_to_dml_params()
1687 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); in dcn20_populate_dml_pipes_from_context()
1688 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, in dcn20_populate_dml_pipes_from_context()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| D | dml21_translation_helper.c | 688 surface->tiling = gfx9_to_dml2_swizzle_mode(plane_state->tiling_info.gfx9.swizzle); in populate_dml21_surface_config_from_plane_state()
690 surface->tiling = gfx_addr3_to_dml2_swizzle_mode(plane_state->tiling_info.gfx_addr3.swizzle); in populate_dml21_surface_config_from_plane_state()
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