Searched refs:stage1 (Results 1 – 8 of 8) sorted by relevance
16 struct dml2_optimization_stage1_state *state = ¶ms->display_config->stage1; in dml2_top_optimization_init_function_min_clk_for_latency()25 struct dml2_optimization_stage1_state *state = ¶ms->display_config->stage1; in dml2_top_optimization_test_function_min_clk_for_latency()34 if (params->display_config->stage1.min_clk_index_for_latency > 0) { in dml2_top_optimization_optimize_function_min_clk_for_latency()36 params->optimized_display_config->stage1.min_clk_index_for_latency--; in dml2_top_optimization_optimize_function_min_clk_for_latency()179 …l->mode_support_params.min_clk_index = l->next_candidate_display_cfg.stage1.min_clk_index_for_late… in dml2_top_optimization_perform_optimization_phase()220 highest_state = l->cur_candidate_display_cfg.stage1.min_clk_index_for_latency; in dml2_top_optimization_perform_optimization_phase_1()240 l->cur_candidate_display_cfg.stage1.min_clk_index_for_latency = lowest_state; in dml2_top_optimization_perform_optimization_phase_1()
86 …out->stage1.min_clk_index_for_latency = dml->min_clk_table.dram_bw_table.num_entries - 1; //dml->m… in setup_unoptimized_display_config_with_meta()92 out->stage1.min_clk_index_for_latency = 0; in setup_speculative_display_config_with_meta()111 …l->mode_support_params.min_clk_index = l->base_display_config_with_meta.stage1.min_clk_index_for_l… in dml2_check_mode_supported()168 …l->mode_support_params.min_clk_index = l->base_display_config_with_meta.stage1.min_clk_index_for_l… in dml2_build_mode_programming()179 …l->mode_support_params.min_clk_index = l->base_display_config_with_meta.stage1.min_clk_index_for_l… in dml2_build_mode_programming()
514 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; in arm_smmu_init_context_bank() local519 if (stage1) { in arm_smmu_init_context_bank()535 if (stage1) { in arm_smmu_init_context_bank()555 if (stage1) { in arm_smmu_init_context_bank()569 bool stage1; in arm_smmu_write_context_bank() local579 stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; in arm_smmu_write_context_bank()603 if (stage1) { in arm_smmu_write_context_bank()619 if (stage1 && smmu->version > ARM_SMMU_V1) in arm_smmu_write_context_bank()630 if (stage1) in arm_smmu_write_context_bank()636 if (stage1) { in arm_smmu_write_context_bank()[all …]
532 state->min_clk_index_for_latency = in_out->base_display_config->stage1.min_clk_index_for_latency; in pmo_dcn3_init_for_pstate_support()533 …pmo->scratch.pmo_dcn3.min_latency_index = in_out->base_display_config->stage1.min_clk_index_for_la… in pmo_dcn3_init_for_pstate_support()535 …pmo->scratch.pmo_dcn3.cur_latency_index = in_out->base_display_config->stage1.min_clk_index_for_la… in pmo_dcn3_init_for_pstate_support()
1745 …_config->stage3.min_clk_index_for_latency = in_out->base_display_config->stage1.min_clk_index_for_… in pmo_dcn4_fams2_init_for_pstate_support()1756 …pmo->scratch.pmo_dcn4.min_latency_index = in_out->base_display_config->stage1.min_clk_index_for_la… in pmo_dcn4_fams2_init_for_pstate_support()1758 …pmo->scratch.pmo_dcn4.cur_latency_index = in_out->base_display_config->stage1.min_clk_index_for_la… in pmo_dcn4_fams2_init_for_pstate_support()
44 --first-stage-init artifacts/ci-common/init-stage1.sh \
344 struct dml2_optimization_stage1_state stage1; member
32 min_clock_index_for_latency = in_out->display_cfg->stage1.min_clk_index_for_latency; in get_minimum_clocks_for_latency()