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Searched refs:soc_mask (Results 1 – 7 of 7) sorted by relevance

/linux-6.12.1/drivers/clk/ti/
Dclkctrl.c524 u16 soc_mask = 0; in _ti_omap4_clkctrl_setup() local
542 soc_mask = CLKF_SOC_DRA72; in _ti_omap4_clkctrl_setup()
544 soc_mask = CLKF_SOC_DRA74; in _ti_omap4_clkctrl_setup()
546 soc_mask = CLKF_SOC_DRA76; in _ti_omap4_clkctrl_setup()
568 soc_mask |= CLKF_SOC_NONSEC; in _ti_omap4_clkctrl_setup()
648 (reg_data->flags & soc_mask) == 0) { in _ti_omap4_clkctrl_setup()
/linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dvangogh_ppt.c809 uint32_t *soc_mask) in vangogh_get_profiling_clk_mask() argument
820 if (soc_mask) in vangogh_get_profiling_clk_mask()
821 *soc_mask = 0; in vangogh_get_profiling_clk_mask()
829 if (soc_mask) in vangogh_get_profiling_clk_mask()
830 *soc_mask = 1; in vangogh_get_profiling_clk_mask()
844 if (soc_mask) in vangogh_get_profiling_clk_mask()
845 *soc_mask = 1; in vangogh_get_profiling_clk_mask()
895 uint32_t soc_mask; in vangogh_get_dpm_ultimate_freq() local
944 &soc_mask); in vangogh_get_dpm_ultimate_freq()
956 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max); in vangogh_get_dpm_ultimate_freq()
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/linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c254 uint32_t *soc_mask) in renoir_get_profiling_clk_mask() argument
273 if (soc_mask) in renoir_get_profiling_clk_mask()
274 *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1; in renoir_get_profiling_clk_mask()
286 uint32_t mclk_mask, soc_mask; in renoir_get_dpm_ultimate_freq() local
321 &soc_mask); in renoir_get_dpm_ultimate_freq()
342 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max); in renoir_get_dpm_ultimate_freq()
/linux-6.12.1/drivers/pinctrl/
Dpinctrl-single.c1405 unsigned soc_mask; in pcs_irq_set() local
1411 soc_mask = pcs_soc->irq_enable_mask; in pcs_irq_set()
1415 mask |= soc_mask; in pcs_irq_set()
1417 mask &= ~soc_mask; in pcs_irq_set()
/linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega12_hwmgr.c1728 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega12_get_profiling_clk_mask() argument
1737 *soc_mask = 0; in vega12_get_profiling_clk_mask()
1744 *soc_mask = VEGA12_UMD_PSTATE_SOCCLK_LEVEL; in vega12_get_profiling_clk_mask()
1754 *soc_mask = soc_dpm_table->count - 1; in vega12_get_profiling_clk_mask()
1784 uint32_t soc_mask = 0; in vega12_dpm_force_dpm_level() local
1800 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega12_dpm_force_dpm_level()
Dvega20_hwmgr.c2534 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega20_get_profiling_clk_mask() argument
2543 *soc_mask = 0; in vega20_get_profiling_clk_mask()
2550 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL; in vega20_get_profiling_clk_mask()
2560 *soc_mask = soc_dpm_table->count - 1; in vega20_get_profiling_clk_mask()
2734 uint32_t sclk_mask, mclk_mask, soc_mask; in vega20_dpm_force_dpm_level() local
2753 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega20_dpm_force_dpm_level()
2758 vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask); in vega20_dpm_force_dpm_level()
Dvega10_hwmgr.c4220 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega10_get_profiling_clk_mask() argument
4229 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL; in vega10_get_profiling_clk_mask()
4245 *soc_mask = table_info->vdd_dep_on_socclk->count - 1; in vega10_get_profiling_clk_mask()
4339 uint32_t soc_mask = 0; in vega10_dpm_force_dpm_level() local
4355 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()