Searched refs:smpl_phase (Results 1 – 2 of 2) sorted by relevance
42 static void dw_mci_starfive_set_sample_phase(struct dw_mci *host, u32 smpl_phase) in dw_mci_starfive_set_sample_phase() argument49 reg_value |= FIELD_PREP(STARFIVE_SMPL_PHASE, smpl_phase); in dw_mci_starfive_set_sample_phase()61 int smpl_phase, smpl_raise = -1, smpl_fall = -1; in dw_mci_starfive_execute_tuning() local64 for (smpl_phase = 0; smpl_phase < grade; smpl_phase++) { in dw_mci_starfive_execute_tuning()65 dw_mci_starfive_set_sample_phase(host, smpl_phase); in dw_mci_starfive_execute_tuning()71 smpl_raise = smpl_phase; in dw_mci_starfive_execute_tuning()73 smpl_fall = smpl_phase - 1; in dw_mci_starfive_execute_tuning()78 if (smpl_phase >= grade) in dw_mci_starfive_execute_tuning()82 smpl_phase = 0; in dw_mci_starfive_execute_tuning()88 smpl_phase = (smpl_raise + smpl_fall) / 2; in dw_mci_starfive_execute_tuning()[all …]
217 int smpl_phase) in dw_mci_hs_set_timing() argument232 if (smpl_phase == -1) in dw_mci_hs_set_timing()233 smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max + in dw_mci_hs_set_timing()238 if (smpl_phase >= USE_DLY_MIN_SMPL && in dw_mci_hs_set_timing()239 smpl_phase <= USE_DLY_MAX_SMPL) in dw_mci_hs_set_timing()243 if (smpl_phase >= ENABLE_SHIFT_MIN_SMPL && in dw_mci_hs_set_timing()244 smpl_phase <= ENABLE_SHIFT_MAX_SMPL) in dw_mci_hs_set_timing()252 reg_value = FIELD_PREP(UHS_REG_EXT_SAMPLE_PHASE_MASK, smpl_phase) | in dw_mci_hs_set_timing()372 int smpl_phase = 0; in dw_mci_hi3660_execute_tuning() local376 for (i = 0; i < NUM_PHASES; ++i, ++smpl_phase) { in dw_mci_hi3660_execute_tuning()[all …]