/linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
D | tonga_smumgr.c | 530 smu_data->smc_state_table.LinkLevelCount = in tonga_populate_smc_link_level() 700 SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; in tonga_populate_all_graphic_levels() 713 &(smu_data->smc_state_table.GraphicsLevel[i])); in tonga_populate_all_graphic_levels() 719 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in tonga_populate_all_graphic_levels() 723 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in tonga_populate_all_graphic_levels() 727 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in tonga_populate_all_graphic_levels() 730 smu_data->smc_state_table.GraphicsDpmLevelCount = in tonga_populate_all_graphic_levels() 741 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = in tonga_populate_all_graphic_levels() 771 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; in tonga_populate_all_graphic_levels() 774 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; in tonga_populate_all_graphic_levels() [all …]
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D | fiji_smumgr.c | 490 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in fiji_populate_bapm_parameters_in_dpm_table() 847 smu_data->smc_state_table.LinkLevelCount = in fiji_populate_smc_link_level() 1015 smu_data->smc_state_table.GraphicsLevel; in fiji_populate_all_graphic_levels() 1041 smu_data->smc_state_table.GraphicsDpmLevelCount = in fiji_populate_all_graphic_levels() 1231 smu_data->smc_state_table.MemoryLevel; in fiji_populate_all_memory_levels() 1256 smu_data->smc_state_table.MemoryDpmLevelCount = in fiji_populate_all_memory_levels() 1643 smu_data->smc_state_table.GraphicsBootLevel = level; in fiji_populate_smc_initailial_state() 1652 smu_data->smc_state_table.MemoryBootLevel = level; in fiji_populate_smc_initailial_state() 1697 smu_data->smc_state_table.ClockStretcherAmount = stretch_amount; in fiji_populate_clock_stretcher_data_table() 1701 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |= in fiji_populate_clock_stretcher_data_table() [all …]
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D | polaris10_smumgr.c | 432 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); in polaris10_populate_bapm_parameters_in_dpm_table() 478 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); in polaris10_populate_zero_rpm_parameters() 836 smu_data->smc_state_table.LinkLevelCount = in polaris10_populate_smc_link_level() 894 const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); in polaris10_calculate_sclk_params() 1029 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); in polaris10_get_vddc_shared_railinfo() 1051 smu_data->smc_state_table.GraphicsLevel; in polaris10_populate_all_graphic_levels() 1065 polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table)); in polaris10_populate_all_graphic_levels() 1071 &(smu_data->smc_state_table.GraphicsLevel[i])); in polaris10_populate_all_graphic_levels() 1081 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0; in polaris10_populate_all_graphic_levels() 1097 smu_data->smc_state_table.GraphicsDpmLevelCount = in polaris10_populate_all_graphic_levels() [all …]
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D | ci_smumgr.c | 483 smu_data->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels() 493 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels() 495 smu_data->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels() 499 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels() 501 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels() 720 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in ci_populate_bapm_parameters_in_dpm_table() 1015 smu_data->smc_state_table.LinkLevelCount = in ci_populate_smc_link_level() 1311 SMU7_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels() 1320 &(smu_data->smc_state_table.MemoryLevel[i])); in ci_populate_all_memory_levels() 1325 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels() [all …]
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D | vegam_smumgr.c | 337 smu_data->smc_state_table.UvdBootLevel = 0; in vegam_update_uvd_smc_table() 339 smu_data->smc_state_table.UvdBootLevel = in vegam_update_uvd_smc_table() 348 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; in vegam_update_uvd_smc_table() 358 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel), in vegam_update_uvd_smc_table() 372 smu_data->smc_state_table.VceBootLevel = in vegam_update_vce_smc_table() 375 smu_data->smc_state_table.VceBootLevel = 0; in vegam_update_vce_smc_table() 384 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16; in vegam_update_vce_smc_table() 391 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel, in vegam_update_vce_smc_table() 590 smu_data->smc_state_table.LinkLevelCount = in vegam_populate_smc_link_level() 723 const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table); in vegam_calculate_sclk_params() [all …]
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D | iceland_smumgr.c | 787 smu_data->smc_state_table.LinkLevelCount = in iceland_populate_smc_link_level() 970 SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; in iceland_populate_all_graphic_levels() 983 &(smu_data->smc_state_table.GraphicsLevel[i])); in iceland_populate_all_graphic_levels() 989 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in iceland_populate_all_graphic_levels() 993 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in iceland_populate_all_graphic_levels() 997 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in iceland_populate_all_graphic_levels() 1000 smu_data->smc_state_table.GraphicsDpmLevelCount = in iceland_populate_all_graphic_levels() 1027 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; in iceland_populate_all_graphic_levels() 1031 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; in iceland_populate_all_graphic_levels() 1034 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; in iceland_populate_all_graphic_levels() [all …]
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D | fiji_smumgr.h | 42 struct SMU73_Discrete_DpmTable smc_state_table; member
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D | polaris10_smumgr.h | 57 SMU74_Discrete_DpmTable smc_state_table; member
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D | iceland_smumgr.h | 62 struct SMU71_Discrete_DpmTable smc_state_table; member
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D | vegam_smumgr.h | 66 SMU75_Discrete_DpmTable smc_state_table; member
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D | ci_smumgr.h | 68 struct SMU7_Discrete_DpmTable smc_state_table; member
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D | tonga_smumgr.h | 66 struct SMU72_Discrete_DpmTable smc_state_table; member
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/linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
D | vega10_hwmgr.c | 965 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega10_setup_dpm_led_config() 1483 data->smc_state_table.pp_table.UlvOffsetVid = in vega10_populate_ulv_state() 1486 data->smc_state_table.pp_table.UlvSmnclkDid = in vega10_populate_ulv_state() 1488 data->smc_state_table.pp_table.UlvMp1clkDid = in vega10_populate_ulv_state() 1490 data->smc_state_table.pp_table.UlvGfxclkBypass = in vega10_populate_ulv_state() 1492 data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 = in vega10_populate_ulv_state() 1494 data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 = in vega10_populate_ulv_state() 1523 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega10_override_pcie_parameters() 1570 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega10_populate_smc_link_levels() 1732 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega10_populate_all_graphic_levels() [all …]
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D | vega10_thermal.c | 510 PPTable_t *table = &(data->smc_state_table.pp_table); in vega10_thermal_setup_fan_table() 555 (uint8_t *)(&(data->smc_state_table.pp_table)), in vega10_thermal_setup_fan_table() 566 PPTable_t *table = &(data->smc_state_table.pp_table); in vega10_enable_mgpu_fan_boost() 580 (uint8_t *)(&(data->smc_state_table.pp_table)), in vega10_enable_mgpu_fan_boost()
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D | vega12_thermal.c | 256 PPTable_t *table = &(data->smc_state_table.pp_table); in vega12_thermal_setup_fan_table()
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D | vega20_thermal.c | 327 PPTable_t *table = &(data->smc_state_table.pp_table); in vega20_thermal_setup_fan_table()
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D | vega20_hwmgr.c | 795 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega20_init_smc_table() 846 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega20_override_pcie_parameters() 1053 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega20_od8_set_feature_capabilities() 1254 OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table); in vega20_od8_initialize_default_settings() 1355 od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100; in vega20_od8_initialize_default_settings() 2952 Watermarks_t *table = &(data->smc_state_table.water_marks_table); in vega20_set_watermarks_for_clocks_ranges() 2975 &(data->smc_state_table.overdrive_table); in vega20_odn_edit_dpm_table() 3373 &(data->smc_state_table.overdrive_table); in vega20_print_clock_levels() 3374 PPTable_t *pptable = &(data->smc_state_table.pp_table); in vega20_print_clock_levels() 3656 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega20_display_configuration_changed_task() [all …]
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D | vega12_hwmgr.h | 392 struct vega12_smc_state_table smc_state_table; member
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D | vega10_hwmgr.h | 381 struct vega10_smc_state_table smc_state_table; member
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D | vega20_hwmgr.h | 520 struct vega20_smc_state_table smc_state_table; member
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D | vega12_hwmgr.c | 500 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega12_override_pcie_parameters() 825 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega12_init_smc_table() 2011 Watermarks_t *table = &(data->smc_state_table.water_marks_table); in vega12_set_watermarks_for_clocks_ranges() 2563 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega12_display_configuration_changed_task() 2780 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega12_get_thermal_temperature_range()
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D | vega10_powertune.c | 1242 PPTable_t *table = &(data->smc_state_table.pp_table); in vega10_initialize_power_tune_defaults()
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D | smu7_hwmgr.c | 5338 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); in smu7_set_watermarks_for_clocks_ranges()
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/linux-6.12.1/drivers/gpu/drm/radeon/ |
D | ci_dpm.c | 405 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table() 1275 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits() 2552 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state() 2560 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state() 2599 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level() 3240 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels() 3249 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels() 3253 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels() 3255 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels() 3258 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels() [all …]
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D | ci_dpm.h | 222 SMU7_Discrete_DpmTable smc_state_table; member
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