| /linux-6.12.1/crypto/ |
| D | simd.c | 215 struct simd_skcipher_alg *simd; in simd_register_skciphers_compat() local
227 simd = simd_skcipher_create_compat(algs + i, algname, drvname, basename); in simd_register_skciphers_compat()
228 err = PTR_ERR(simd); in simd_register_skciphers_compat()
229 if (IS_ERR(simd)) in simd_register_skciphers_compat()
231 simd_algs[i] = simd; in simd_register_skciphers_compat()
438 struct simd_aead_alg *simd; in simd_register_aeads_compat() local
450 simd = simd_aead_create_compat(algs + i, algname, drvname, basename); in simd_register_aeads_compat()
451 err = PTR_ERR(simd); in simd_register_aeads_compat()
452 if (IS_ERR(simd)) in simd_register_aeads_compat()
454 simd_algs[i] = simd; in simd_register_aeads_compat()
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| D | Makefile | 204 crypto_simd-y := simd.o
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v9_4_2.c | 422 uint32_t se, cu, simd, wave; in gfx_v9_4_2_log_wave_assignment() local
437 for (simd = 0; simd < SIMD_ID_MAX; simd++) { in gfx_v9_4_2_log_wave_assignment()
456 uint32_t se, cu, simd, wave; in gfx_v9_4_2_wait_for_waves_assigned() local
467 for (simd = 0; simd < SIMD_ID_MAX; simd++) in gfx_v9_4_2_wait_for_waves_assigned()
1804 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
1808 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
1818 uint32_t i, simd, wave; in gfx_v9_4_2_log_cu_timeout_status() local
1829 simd = i / cu_info->max_waves_per_simd; in gfx_v9_4_2_log_cu_timeout_status()
1832 wave_status = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_2_log_cu_timeout_status()
1833 wave_pc_lo = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_4_2_log_cu_timeout_status()
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| D | gfx_v6_0.c | 2945 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
2949 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
2955 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
2961 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
2970 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v6_0_read_wave_data() argument
2974 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v6_0_read_wave_data()
2975 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v6_0_read_wave_data()
2976 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v6_0_read_wave_data()
2977 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v6_0_read_wave_data()
2978 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v6_0_read_wave_data()
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| D | gfx_v7_0.c | 4049 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
4053 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
4059 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
4065 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
4074 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v7_0_read_wave_data() argument
4078 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v7_0_read_wave_data()
4079 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v7_0_read_wave_data()
4080 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v7_0_read_wave_data()
4081 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v7_0_read_wave_data()
4082 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v7_0_read_wave_data()
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| D | amdgpu_umr.h | 50 u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id; member
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| D | amdgpu_debugfs.c | 434 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); in amdgpu_debugfs_gprwave_read()
439 …adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread,… in amdgpu_debugfs_gprwave_read()
442 …adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, dat… in amdgpu_debugfs_gprwave_read()
1061 uint32_t offset, se, sh, cu, wave, simd, data[32]; in amdgpu_debugfs_wave_read() local
1072 simd = (*pos & GENMASK_ULL(44, 37)) >> 37; in amdgpu_debugfs_wave_read()
1092 adev->gfx.funcs->read_wave_data(adev, 0, simd, wave, data, &x); in amdgpu_debugfs_wave_read()
1153 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; in amdgpu_debugfs_gpr_read() local
1164 simd = (*pos & GENMASK_ULL(51, 44)) >> 44; in amdgpu_debugfs_gpr_read()
1186 adev->gfx.funcs->read_wave_vgprs(adev, 0, simd, wave, thread, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
1189 adev->gfx.funcs->read_wave_sgprs(adev, 0, simd, wave, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
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| D | amdgpu_gfx.h | 292 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
294 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
297 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
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| D | gfx_v9_4_3.c | 719 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t … in wave_read_ind() argument
723 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
729 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in wave_read_regs() argument
735 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
745 uint32_t xcc_id, uint32_t simd, uint32_t wave, in gfx_v9_4_3_read_wave_data() argument
750 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_3_read_wave_data()
751 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_4_3_read_wave_data()
752 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_4_3_read_wave_data()
753 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_4_3_read_wave_data()
754 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_4_3_read_wave_data()
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| D | gfx_v8_0.c | 5189 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
5193 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
5199 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
5205 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
5214 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v8_0_read_wave_data() argument
5218 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v8_0_read_wave_data()
5219 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v8_0_read_wave_data()
5220 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v8_0_read_wave_data()
5221 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v8_0_read_wave_data()
5222 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v8_0_read_wave_data()
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| D | gfx_v9_0.c | 1918 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
1922 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
1928 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
1934 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
1943 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v9_0_read_wave_data() argument
1947 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_0_read_wave_data()
1948 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_0_read_wave_data()
1949 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_0_read_wave_data()
1950 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_0_read_wave_data()
1951 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_0_read_wave_data()
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| D | gfx_v12_0.c | 799 uint32_t simd, uint32_t wave, in gfx_v12_0_read_wave_data() argument
805 WARN_ON(simd != 0); in gfx_v12_0_read_wave_data()
835 uint32_t xcc_id, uint32_t simd, in gfx_v12_0_read_wave_sgprs() argument
839 WARN_ON(simd != 0); in gfx_v12_0_read_wave_sgprs()
847 uint32_t xcc_id, uint32_t simd, in gfx_v12_0_read_wave_vgprs() argument
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| D | gfx_v11_0.c | 971 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, ui… in gfx_v11_0_read_wave_data() argument
976 WARN_ON(simd != 0); in gfx_v11_0_read_wave_data()
997 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_sgprs() argument
1001 WARN_ON(simd != 0); in gfx_v11_0_read_wave_sgprs()
1008 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_vgprs() argument
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| D | gfx_v10_0.c | 4432 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, ui… in gfx_v10_0_read_wave_data() argument
4438 WARN_ON(simd != 0); in gfx_v10_0_read_wave_data()
4460 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v10_0_read_wave_sgprs() argument
4464 WARN_ON(simd != 0); in gfx_v10_0_read_wave_sgprs()
4471 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v10_0_read_wave_vgprs() argument
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| /linux-6.12.1/arch/arm/crypto/ |
| D | aes-neonbs-glue.c | 473 struct simd_skcipher_alg *simd; in aes_init() local
494 simd = simd_skcipher_create_compat(aes_algs + i, algname, drvname, basename); in aes_init()
495 err = PTR_ERR(simd); in aes_init()
496 if (IS_ERR(simd)) in aes_init()
499 aes_simd_algs[i] = simd; in aes_init()
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| D | aes-ce-glue.c | 696 struct simd_skcipher_alg *simd; in aes_init() local
714 simd = simd_skcipher_create_compat(aes_algs + i, algname, drvname, basename); in aes_init()
715 err = PTR_ERR(simd); in aes_init()
716 if (IS_ERR(simd)) in aes_init()
719 aes_simd_algs[i] = simd; in aes_init()
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| /linux-6.12.1/include/asm-generic/ |
| D | Kbuild | 53 mandatory-y += simd.h
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| /linux-6.12.1/tools/perf/Documentation/ |
| D | perf-report.txt | 120 …- simd: Flags describing a SIMD operation. "e" for empty Arm SVE predicate. "p" for partial Arm SV…
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