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/linux-6.12.1/drivers/pinctrl/renesas/
Dsh_pfc.h442 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
443 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
444 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument
446 #define PORT_GP_CFG_2(bank, fn, sfx, cfg) \ argument
447 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
448 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
449 #define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0) argument
451 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
452 PORT_GP_CFG_2(bank, fn, sfx, cfg), \
453 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
[all …]
Dpfc-r8a73a4.c13 #define CPU_ALL_PORT(fn, pfx, sfx) \ argument
15 PORT_10(0, fn, pfx, sfx), \
16 PORT_10(10, fn, pfx##1, sfx), \
17 PORT_10(20, fn, pfx##2, sfx), \
18 PORT_1(30, fn, pfx##30, sfx), \
20 PORT_1(32, fn, pfx##32, sfx), PORT_1(33, fn, pfx##33, sfx), \
21 PORT_1(34, fn, pfx##34, sfx), PORT_1(35, fn, pfx##35, sfx), \
22 PORT_1(36, fn, pfx##36, sfx), PORT_1(37, fn, pfx##37, sfx), \
23 PORT_1(38, fn, pfx##38, sfx), PORT_1(39, fn, pfx##39, sfx), \
24 PORT_1(40, fn, pfx##40, sfx), \
[all …]
Dpfc-r8a779a0.c18 #define CPU_ALL_GP(fn, sfx) \ argument
19 PORT_GP_CFG_15(0, fn, sfx, CFG_FLAGS), \
20 PORT_GP_CFG_1(0, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_1(0, 16, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
22 PORT_GP_CFG_1(0, 17, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
23 PORT_GP_CFG_1(0, 18, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
24 PORT_GP_CFG_1(0, 19, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
25 PORT_GP_CFG_1(0, 20, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
26 PORT_GP_CFG_1(0, 21, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
27 PORT_GP_CFG_1(0, 22, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
[all …]
Dpfc-sh73a0.c18 #define CPU_ALL_PORT(fn, pfx, sfx) \ argument
19 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
20 PORT_10(100, fn, pfx##10, sfx), \
21 PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \
22 PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \
23 PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \
24 PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx), \
25 PORT_1(118, fn, pfx##118, sfx), \
26 PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
27 PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx), \
[all …]
Dpfc-emev2.c11 #define CPU_ALL_PORT(fn, pfx, sfx) \ argument
12 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
13 PORT_10(100, fn, pfx##10, sfx), PORT_10(110, fn, pfx##11, sfx), \
14 PORT_10(120, fn, pfx##12, sfx), PORT_10(130, fn, pfx##13, sfx), \
15 PORT_10(140, fn, pfx##14, sfx), PORT_1(150, fn, pfx##150, sfx), \
16 PORT_1(151, fn, pfx##151, sfx), PORT_1(152, fn, pfx##152, sfx), \
17 PORT_1(153, fn, pfx##153, sfx), PORT_1(154, fn, pfx##154, sfx), \
18 PORT_1(155, fn, pfx##155, sfx), PORT_1(156, fn, pfx##156, sfx), \
19 PORT_1(157, fn, pfx##157, sfx), PORT_1(158, fn, pfx##158, sfx)
244 #define __PIN_CFG(pn, pfx, sfx) SH_PFC_PIN_CFG(pfx, 0) argument
[all …]
Dpfc-r8a77470.c13 #define CPU_ALL_GP(fn, sfx) \ argument
14 PORT_GP_CFG_4(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
15 PORT_GP_CFG_1(0, 4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
16 PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
17 PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
18 PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
19 PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
20 PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
21 PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
22 PORT_GP_CFG_1(0, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
[all …]
Dpfc-r8a7794.c17 #define CPU_ALL_GP(fn, sfx) \ argument
18 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
19 PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
20 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
21 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
22 PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
23 PORT_GP_CFG_7(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
24 PORT_GP_1(5, 7, fn, sfx), \
25 PORT_GP_1(5, 8, fn, sfx), \
26 PORT_GP_1(5, 9, fn, sfx), \
[all …]
Dpfc-r8a7779.c14 #define CPU_ALL_GP(fn, sfx) \ argument
15 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
16 PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
17 PORT_GP_CFG_1(2, 0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
18 PORT_GP_1(2, 1, fn, sfx), \
19 PORT_GP_1(2, 2, fn, sfx), \
20 PORT_GP_1(2, 3, fn, sfx), \
21 PORT_GP_1(2, 4, fn, sfx), \
22 PORT_GP_1(2, 5, fn, sfx), \
23 PORT_GP_1(2, 6, fn, sfx), \
[all …]
Dpfc-r8a779h0.c18 #define CPU_ALL_GP(fn, sfx) \ argument
19 PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
20 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_1(1, 29, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_16(2, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_13(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
26 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
[all …]
/linux-6.12.1/arch/arm64/include/asm/
Dcmpxchg.h21 #define __XCHG_CASE(w, sfx, name, sz, mb, nop_lse, acq, acq_lse, rel, cl) \ argument
30 "1: ld" #acq "xr" #sfx "\t%" #w "0, %2\n" \
31 " st" #rel "xr" #sfx "\t%w1, %" #w "3, %2\n" \
35 " swp" #acq_lse #rel #sfx "\t%" #w "3, %" #w "0, %2\n" \
64 #define __XCHG_GEN(sfx) \ argument
66 __arch_xchg##sfx(unsigned long x, volatile void *ptr, int size) \
70 return __xchg_case##sfx##_8(x, ptr); \
72 return __xchg_case##sfx##_16(x, ptr); \
74 return __xchg_case##sfx##_32(x, ptr); \
76 return __xchg_case##sfx##_64(x, ptr); \
[all …]
Drwonce.h16 #define __LOAD_RCPC(sfx, regs...) \ argument
18 "ldar" #sfx "\t" #regs, \
20 "ldapr" #sfx "\t" #regs, \
23 #define __LOAD_RCPC(sfx, regs...) "ldar" #sfx "\t" #regs argument
Dpercpu.h66 #define __PERCPU_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \ argument
75 "1: ldxr" #sfx "\t%" #w "[tmp], %[ptr]\n" \
77 " stxr" #sfx "\t%w[loop], %" #w "[tmp], %[ptr]\n" \
87 #define __PERCPU_RET_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \ argument
96 "1: ldxr" #sfx "\t%" #w "[ret], %[ptr]\n" \
98 " stxr" #sfx "\t%w[loop], %" #w "[ret], %[ptr]\n" \
/linux-6.12.1/scripts/atomic/
Datomic-tbl.sh51 local sfx="$1"; shift
62 for base in "${pfx}${name}${sfx}${order}" "${pfx}${name}${sfx}" "${name}"; do
193 local sfx="$1"; shift
198 local atomicname="${atomic}_${pfx}${name}${sfx}${order}"
234 local sfx="$1"; shift
237 local atomicname="${atomic}_${pfx}${name}${sfx}${order}"
239 local tmpl="$(find_kerneldoc_template "${pfx}" "${name}" "${sfx}" "${order}")"
245 gen_template_kerneldoc "${tmpl}" "${class}" "${meta}" "${pfx}" "${name}" "${sfx}" "${order}" "$@"
255 local sfx="$1"; shift
257 gen_proto_order_variant "${meta}" "${pfx}" "${name}" "${sfx}" "" "$@"
[all …]
Dgen-atomic-fallback.sh15 local sfx="$1"; shift
34 local sfx="$1"; shift
39 gen_template_fallback "${tmpl}" "${meta}" "${pfx}" "${name}" "${sfx}" "${order}" "$@"
48 local sfx="$1"; shift
51 local tmpl="$(find_fallback_template "${pfx}" "${name}" "${sfx}" "${order}")"
52 gen_template_fallback "${tmpl}" "${meta}" "${pfx}" "${name}" "${sfx}" "${order}" "$@"
61 local sfx="$1"; shift
66 local atomicname="${atomic}_${pfx}${name}${sfx}${order}"
67 local basename="${atomic}_${pfx}${name}${sfx}"
69 local template="$(find_fallback_template "${pfx}" "${name}" "${sfx}" "${order}")"
[all …]
Dgen-atomic-long.sh41 local sfx="$1"; shift
44 local atomicname="${pfx}${name}${sfx}${order}"
52 gen_kerneldoc "raw_" "${meta}" "${pfx}" "${name}" "${sfx}" "${order}" "atomic_long" "long" "$@"
Dgen-atomic-instrumented.sh58 local sfx="$1"; shift
63 local atomicname="${atomic}_${pfx}${name}${sfx}${order}"
71 gen_kerneldoc "" "${meta}" "${pfx}" "${name}" "${sfx}" "${order}" "${atomic}" "${int}" "$@"
/linux-6.12.1/arch/riscv/include/asm/
Datomic.h198 #define _arch_atomic_fetch_add_unless(_prev, _rc, counter, _a, _u, sfx) \ argument
201 "0: lr." sfx " %[p], %[c]\n" \
204 " sc." sfx ".rl %[rc], %[rc], %[c]\n" \
237 #define _arch_atomic_inc_unless_negative(_prev, _rc, counter, sfx) \ argument
240 "0: lr." sfx " %[p], %[c]\n" \
243 " sc." sfx ".rl %[rc], %[rc], %[c]\n" \
263 #define _arch_atomic_dec_unless_positive(_prev, _rc, counter, sfx) \ argument
266 "0: lr." sfx " %[p], %[c]\n" \
269 " sc." sfx ".rl %[rc], %[rc], %[c]\n" \
289 #define _arch_atomic_dec_if_positive(_prev, _rc, counter, sfx) \ argument
[all …]
/linux-6.12.1/include/linux/
Dbtree-type.h2 #define __BTREE_TP(pfx, type, sfx) pfx ## type ## sfx argument
3 #define _BTREE_TP(pfx, type, sfx) __BTREE_TP(pfx, type, sfx) argument
/linux-6.12.1/tools/testing/selftests/net/netfilter/
Drpath.sh35 sfx=$(mktemp -u "XXXXXXXX")
36 ns1="ns1-$sfx"
37 ns2="ns2-$sfx"
Dnft_audit.sh57 [[ "$pfx $sfx" == "$tpfx $tsfx" ]] && {
64 tsfx="$sfx"
/linux-6.12.1/scripts/atomic/fallbacks/
Ddec2 ${retstmt}raw_${atomic}_${pfx}sub${sfx}${order}(1, v);
Dinc2 ${retstmt}raw_${atomic}_${pfx}add${sfx}${order}(1, v);
Drelease3 ${retstmt}arch_${atomic}_${pfx}${name}${sfx}_relaxed(${args});
Dandnot2 ${retstmt}raw_${atomic}_${pfx}and${sfx}${order}(~i, v);
Dacquire2 ${ret} ret = arch_${atomic}_${pfx}${name}${sfx}_relaxed(${args});

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