Searched refs:set_hard_min_fclk_by_freq (Results 1 – 8 of 8) sorted by relevance
261 if (pp_smu->set_hard_min_fclk_by_freq && in rv1_update_clocks()264 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()281 if (pp_smu->set_hard_min_fclk_by_freq && in rv1_update_clocks()284 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
130 void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz); member
1356 if (hwmgr->hwmgr_func->set_hard_min_fclk_by_freq == NULL) { in pp_set_hard_min_fclk_by_freq()1361 hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock); in pp_set_hard_min_fclk_by_freq()1638 .set_hard_min_fclk_by_freq = pp_set_hard_min_fclk_by_freq,
770 funcs->rv_funcs.set_hard_min_fclk_by_freq = in dm_pp_get_funcs()
1809 if (!pp_funcs->set_hard_min_fclk_by_freq) in amdgpu_dpm_set_hard_min_fclk_by_freq()1813 pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, in amdgpu_dpm_set_hard_min_fclk_by_freq()
440 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); member
351 int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock); member
1678 .set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq,