| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v9_4.c | 693 uint32_t sec_count, ded_count; in gfx_v9_4_query_utc_edc_status() local
711 sec_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, SEC_COUNT); in gfx_v9_4_query_utc_edc_status()
712 if (sec_count) { in gfx_v9_4_query_utc_edc_status()
715 vml2_mems[i], sec_count); in gfx_v9_4_query_utc_edc_status()
716 err_data->ce_count += sec_count; in gfx_v9_4_query_utc_edc_status()
732 sec_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL, in gfx_v9_4_query_utc_edc_status()
734 if (sec_count) { in gfx_v9_4_query_utc_edc_status()
737 vml2_walker_mems[i], sec_count); in gfx_v9_4_query_utc_edc_status()
738 err_data->ce_count += sec_count; in gfx_v9_4_query_utc_edc_status()
755 sec_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, SEC_COUNT); in gfx_v9_4_query_utc_edc_status()
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| D | sdma_v4_4.c | 170 uint32_t *sec_count) in sdma_v4_4_get_ras_error_count() argument
190 *sec_count += sec_cnt; in sdma_v4_4_get_ras_error_count()
200 uint32_t sec_count = 0; in sdma_v4_4_query_ras_error_count_by_instance() local
209 instance, &sec_count); in sdma_v4_4_query_ras_error_count_by_instance()
216 instance, &sec_count); in sdma_v4_4_query_ras_error_count_by_instance()
225 err_data->ue_count += sec_count; in sdma_v4_4_query_ras_error_count_by_instance()
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| D | gfx_v9_4_2.c | 1453 uint32_t value, uint32_t *sec_count, in gfx_v9_4_2_get_reg_error_count() argument
1472 *sec_count += sec_cnt; in gfx_v9_4_2_get_reg_error_count()
1490 uint32_t *sec_count, uint32_t *ded_count) in gfx_v9_4_2_query_sram_edc_count() argument
1495 if (sec_count && ded_count) { in gfx_v9_4_2_query_sram_edc_count()
1496 *sec_count = 0; in gfx_v9_4_2_query_sram_edc_count()
1509 if (!sec_count || !ded_count) { in gfx_v9_4_2_query_sram_edc_count()
1532 if (sec_count && ded_count) { in gfx_v9_4_2_query_sram_edc_count()
1533 *sec_count += sec_cnt; in gfx_v9_4_2_query_sram_edc_count()
1595 uint32_t *sec_count, in gfx_v9_4_2_query_utc_edc_count() argument
1603 if (sec_count && ded_count) { in gfx_v9_4_2_query_utc_edc_count()
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| D | mmhub_v1_0.c | 710 uint32_t value, uint32_t *sec_count, uint32_t *ded_count) in mmhub_v1_0_get_ras_error_count() argument
727 *sec_count += sec_cnt; in mmhub_v1_0_get_ras_error_count()
749 uint32_t sec_count = 0, ded_count = 0; in mmhub_v1_0_query_ras_error_count() local
762 reg_value, &sec_count, &ded_count); in mmhub_v1_0_query_ras_error_count()
765 err_data->ce_count += sec_count; in mmhub_v1_0_query_ras_error_count()
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| D | mmhub_v1_7.c | 1209 uint32_t *sec_count, in mmhub_v1_7_get_ras_error_count() argument
1226 *sec_count += sec_cnt; in mmhub_v1_7_get_ras_error_count()
1247 uint32_t sec_count = 0, ded_count = 0; in mmhub_v1_7_query_ras_error_count() local
1259 reg_value, &sec_count, &ded_count); in mmhub_v1_7_query_ras_error_count()
1262 err_data->ce_count += sec_count; in mmhub_v1_7_query_ras_error_count()
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| D | mmhub_v9_4.c | 1564 uint32_t *sec_count, in mmhub_v9_4_get_ras_error_count() argument
1581 *sec_count += sec_cnt; in mmhub_v9_4_get_ras_error_count()
1602 uint32_t sec_count = 0, ded_count = 0; in mmhub_v9_4_query_ras_error_count() local
1614 reg_value, &sec_count, &ded_count); in mmhub_v9_4_query_ras_error_count()
1617 err_data->ce_count += sec_count; in mmhub_v9_4_query_ras_error_count()
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| D | gfx_v9_0.c | 6860 uint32_t sec_count, ded_count; in gfx_v9_0_query_utc_edc_status() local
6875 sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT); in gfx_v9_0_query_utc_edc_status()
6876 if (sec_count) { in gfx_v9_0_query_utc_edc_status()
6878 "SEC %d\n", i, vml2_mems[i], sec_count); in gfx_v9_0_query_utc_edc_status()
6879 err_data->ce_count += sec_count; in gfx_v9_0_query_utc_edc_status()
6894 sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, in gfx_v9_0_query_utc_edc_status()
6896 if (sec_count) { in gfx_v9_0_query_utc_edc_status()
6898 "SEC %d\n", i, vml2_walker_mems[i], sec_count); in gfx_v9_0_query_utc_edc_status()
6899 err_data->ce_count += sec_count; in gfx_v9_0_query_utc_edc_status()
6915 sec_count = (data & 0x00006000L) >> 0xd; in gfx_v9_0_query_utc_edc_status()
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| D | sdma_v4_0.c | 2646 uint32_t *sec_count) in sdma_v4_0_get_ras_error_count() argument
2663 *sec_count += sec_cnt; in sdma_v4_0_get_ras_error_count()
2672 uint32_t sec_count = 0; in sdma_v4_0_query_ras_error_count_by_instance() local
2679 instance, &sec_count); in sdma_v4_0_query_ras_error_count_by_instance()
2682 err_data->ce_count += sec_count; in sdma_v4_0_query_ras_error_count_by_instance()
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| /linux-6.12.1/drivers/gpu/drm/msm/adreno/ |
| D | a6xx_gmu.c | 1316 size_t pri_count, sec_count; in a6xx_gmu_rpmh_arc_votes_init() local
1333 sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); in a6xx_gmu_rpmh_arc_votes_init()
1335 sec = cmd_db_read_aux_data("mx.lvl", &sec_count); in a6xx_gmu_rpmh_arc_votes_init()
1339 sec_count >>= 1; in a6xx_gmu_rpmh_arc_votes_init()
1340 if (!sec_count) in a6xx_gmu_rpmh_arc_votes_init()
1372 for (j = 0; j < sec_count; j++) { in a6xx_gmu_rpmh_arc_votes_init()
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