| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | si_dma.c | 585 u32 sdma_cntl; in si_dma_set_trap_irq_state() local
591 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
592 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
593 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
596 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
597 sdma_cntl |= TRAP_ENABLE; in si_dma_set_trap_irq_state()
598 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
607 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
608 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
609 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
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| D | sdma_v2_4.c | 993 u32 sdma_cntl; in sdma_v2_4_set_trap_irq_state() local
999 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1000 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
1001 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1004 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1005 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
1006 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1015 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1016 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
1017 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
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| D | sdma_v3_0.c | 1329 u32 sdma_cntl; in sdma_v3_0_set_trap_irq_state() local
1335 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1336 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1337 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1340 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1341 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
1342 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1351 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1352 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1353 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
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| D | cik_sdma.c | 1102 u32 sdma_cntl; in cik_sdma_set_trap_irq_state() local
1108 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1109 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; in cik_sdma_set_trap_irq_state()
1110 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1113 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1114 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; in cik_sdma_set_trap_irq_state()
1115 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1124 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1125 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; in cik_sdma_set_trap_irq_state()
1126 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
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| D | sdma_v4_4_2.c | 1574 u32 sdma_cntl; in sdma_v4_4_2_set_trap_irq_state() local
1576 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); in sdma_v4_4_2_set_trap_irq_state()
1577 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, in sdma_v4_4_2_set_trap_irq_state()
1579 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); in sdma_v4_4_2_set_trap_irq_state()
1670 u32 sdma_cntl; in sdma_v4_4_2_set_ecc_irq_state() local
1672 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); in sdma_v4_4_2_set_ecc_irq_state()
1673 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE, in sdma_v4_4_2_set_ecc_irq_state()
1675 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); in sdma_v4_4_2_set_ecc_irq_state()
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| D | sdma_v7_0.c | 1467 u32 sdma_cntl; in sdma_v7_0_set_trap_irq_state() local
1471 sdma_cntl = RREG32(reg_offset); in sdma_v7_0_set_trap_irq_state()
1472 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v7_0_set_trap_irq_state()
1474 WREG32(reg_offset, sdma_cntl); in sdma_v7_0_set_trap_irq_state()
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| D | sdma_v6_0.c | 1477 u32 sdma_cntl; in sdma_v6_0_set_trap_irq_state() local
1482 sdma_cntl = RREG32(reg_offset); in sdma_v6_0_set_trap_irq_state()
1483 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v6_0_set_trap_irq_state()
1485 WREG32(reg_offset, sdma_cntl); in sdma_v6_0_set_trap_irq_state()
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| D | sdma_v5_2.c | 1452 u32 sdma_cntl; in sdma_v5_2_set_trap_irq_state() local
1456 sdma_cntl = RREG32(reg_offset); in sdma_v5_2_set_trap_irq_state()
1457 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v5_2_set_trap_irq_state()
1459 WREG32(reg_offset, sdma_cntl); in sdma_v5_2_set_trap_irq_state()
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| D | sdma_v5_0.c | 1587 u32 sdma_cntl; in sdma_v5_0_set_trap_irq_state() local
1594 sdma_cntl = RREG32(reg_offset); in sdma_v5_0_set_trap_irq_state()
1595 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v5_0_set_trap_irq_state()
1597 WREG32(reg_offset, sdma_cntl); in sdma_v5_0_set_trap_irq_state()
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| D | sdma_v4_0.c | 2064 u32 sdma_cntl; in sdma_v4_0_set_trap_irq_state() local
2066 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); in sdma_v4_0_set_trap_irq_state()
2067 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v4_0_set_trap_irq_state()
2069 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); in sdma_v4_0_set_trap_irq_state()
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