Home
last modified time | relevance | path

Searched refs:scratch_reg2 (Results 1 – 10 of 10) sorted by relevance

/linux-6.12.1/arch/x86/entry/
Dcalling.h183 .macro SWITCH_TO_USER_CR3 scratch_reg:req scratch_reg2:req
191 movq \scratch_reg, \scratch_reg2
198 movq \scratch_reg2, \scratch_reg
202 movq \scratch_reg2, \scratch_reg
215 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
217 SWITCH_TO_USER_CR3 \scratch_reg \scratch_reg2
224 SWITCH_TO_USER_CR3 scratch_reg=\scratch_reg scratch_reg2=%rax
281 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
Dentry_64_compat.S274 SWITCH_TO_USER_CR3_NOSTACK scratch_reg=%r8 scratch_reg2=%r9
Dentry_64.S611 SWITCH_TO_USER_CR3 scratch_reg=%rdi scratch_reg2=%rax
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Damdgpu_virt.c1010 void *scratch_reg2; in amdgpu_virt_rlcg_reg_rw() local
1031 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2; in amdgpu_virt_rlcg_reg_rw()
1041 writel(v, scratch_reg2); in amdgpu_virt_rlcg_reg_rw()
Damdgpu_rlc.h253 uint32_t scratch_reg2; member
Dgfx_v9_4_3.c1412 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
Dgfx_v12_0.c698 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); in gfx_v12_0_init_rlcg_reg_access_ctrl()
Dgfx_v11_0.c872 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); in gfx_v11_0_init_rlcg_reg_access_ctrl()
Dgfx_v9_0.c1816 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); in gfx_v9_0_init_rlcg_reg_access_ctrl()
Dgfx_v10_0.c4300 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); in gfx_v10_0_init_rlcg_reg_access_ctrl()